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Web compiler configures embedded memory IP

Posted: 02 Jul 2007     Print Version  Bookmark and Share

Keywords:embedded memory IP  Web-based compiler  IP cores for embedded memory  compiler technology for IP cores 

Novelics Inc. has rolled out a Web-based compiler technology that supports its line of intellectual property (IP) cores for embedded memory applications, reducing the cost and cycle times of IC designs. The technology, dubbed MemQuest, lets designers automatically configure the company's IP with a unified compiler and a common, easy-to-use interface.

The compiler supports and enables Novelics' line of previously announced embedded memory IP, which includes separate cache, flash, ROM, and one- and six-transistor-cell SRAM products. The IP is implemented in a standard logic CMOS process that's said to require no additional masks steps.

A key for the IP is the compiler. Some memory IP suppliers provide only a portion of the compiler technology, forcing customers to generate the IP manually. In those cases, designers can take some four months to devise a circuit or SoC, Novelics said. In contrast, the MemQuest compiler eliminates potential non-recurring engineering fees for manual implementation, said Farzad Zarrinfar, president of Novelics. With MemQuest, IP generation can be handled in a "few minutes," Zarrinfar said.

The compiler provides an automated tool for use in developing ASICs, ASSPs, SoCs and other complex designs. "System designers can make smart technical decisions without making any unnecessary compromises," said Novelics CEO Cyrus Afghahi. MemQuest provides support for embedded memory blocks as large as 32Mbits, with various aspect ratios. Designers can also compile memory blocks with nominal conditions.

Novelics' IP and compiler products are tuned to work with major foundries, such as Silterra, SMIC, TSMC and UMC.

- Mark LaPedus
EE Times

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