Global Sources
EE Times-India
Stay in touch with EE Times India
 
 
Power/Alternative Energy  

Why voltage-aware verification strategy counts

Posted: 25 Nov 2009  Print Version  Bookmark and Share

Keywords:voltage aware verification  verification strategy  low power design 

Low-power design is not new. Extending battery life for mobile devices meant playing design tricks to conserve energy in every possible way. The desire to integrate an SoC and reduce overall cost led designers to rapidly adopt advanced manufacturing processes. The move to smaller manufacturing geometries accelerated the need for low-power design because of the exponential increase in leakage power from smaller transistors packed in ever larger numbers on a single chip.

Governmental regulations have been a more recent driver. Driven by the popularity of green initiatives, specifications have been standardised for power consumption for almost all household electronic gadgets. The regulations impose limits on how much energy a device can consume when it is idle, which has the far reaching effect of extending low-power design to even plugged-in-the wall devices. What is new is that almost all electronic designs are becoming power-managed designs. Verification of low-power designs, which until recently was a challenge for just a handful of all designs, is fast becoming every designer's problem.

Verification impact
Designers employ a wide range of design techniques to manage power. All the techniques focus on one principle: Turn off logic that is not required for the functioning of the chip at a given point in time. Additional design elements and control circuitry are deployed to apply the "off when not needed" principle. In its simplest form, a design is partitioned into a number of power domains that can be independently turned on or off. Any such partitioning requires that the sections of the chip driven by signals in a powered off domain be protected from corrupting signals in an operating domain. More complex techniques rely on changing the voltage and/or the frequency of operation depending on the task that has to be executed by the logic within a power domain. The idea is to supply the minimum voltage necessary to power an operational domain because power consumption is highly affected by voltage. The additional design complexity immediately correlates to new bugs.

Detection of these bugs would have been just a linear extension of the effort involved for non-low-power designs, but for the fact that with each partition of a design into different power domains, the number of combinations that must be considered for verification increases exponentially. First, you have a design that can operate in different functional modes. Then you have each functional mode associated with a power state representing its operating voltage. Finally, you have the design making transitions from one operating mode to another, which may involve one or more transitions of power states in a specific order. Combine all these and you have a perfect verification storm, because now you must verify that the design correctly operates in each functional mode in the corresponding power state and makes the intended transitions in the proper sequence.

Voltage awareness is key
Designs in the non-low power era were voltage agnostic. Even the HDLs described a design state as on (1) or off (0). This simplistic view will not suffice anymore.

Low-power design requires understanding the value of voltages. A design in standby (idle mode) is not set to 0. It is some intermediate value between 0 and the operating voltage. Even the operating voltage changes when techniques such as dynamic voltage scaling are used. Designs are increasingly using multiple supply voltages, whose values are different. Without knowledge of the actual voltage values and the power domains they control, verification results are meaningless and error-ridden. Voltage value-aware verification is a must to avoid nasty surprises in silicon.

Tackling verification complexity
Every new process technology doubles the number of transistors in a given silicon area. If this sounds familiar, it is because this is Moore's Law. Each low power design technique requires monitoring of well-known and understood sequences of events.

For example, power gated designs require that the outputs of a domain be isolated before shutting off the power domain. During simulation, a late isolation enable signal can be automatically monitored at every output of a powered down domain. Verification tools for low power need to incorporate the smarts to profile a design, understand what power management techniques are applied to it, and automatically generate and track the appropriate assertions for such sequences and flag them as errors should they be triggered.

In the absence of such automation, low-power designers and verification teams are stuck with manually generating thousands of assertions hoping to cover every possible sequence at all appropriate points in the design. Being human, it is conceivable that they may miss a few. All it takes is one missed assertion and a little bad luck for the design to fail exactly at the location where an assertion was missed. The moral of this story: You need assertions to manage the design complexity, and you can't leave this to chance. Automation is the answer.

Time to overhaul
Design teams initiating low-power projects are overwhelmed with where to start. First, you need to specify your power intent in a power-intent language. That is because standard HDLs don't effectively allow capture of this information.

The next step is to adapt your existing simulation testbench to be power-aware. Without this step, you are not exercising the design in different power modes and transitions.

Finally, you need to have a way to track your verification progress. For that, automated coverage information specific to low-power tests is a required feature of the verification tool you choose.

Low-power designs differ fundamentally from non-low power designs in how they turn on when powered up. The power-up process may involve different parts of the chip being turned on one at a time and in a specific sequence. Successful power up may depend on the correct power-up sequence because signals from one powered up domain may enable powering up of another domain. Elaborate tests need to be developed to ensure this functionality.

Often, system-level firmware/software may be managing power at the chip level. Without testing the firmware/software interaction, you wouldn't know if your low-power design will work as expected.

Make no mistake about it—low power designs are here to stay. If you continue verification as you did before, you will have to pray a lot for your design to work. A more robust verification strategy is to incorporate a voltage-aware, assertion- and coverage-based verification strategy that includes extensive power-on-reset and firmware tests. At the end of the day, you can either comprehensively verify your next low-power design and rest assured of silicon success or cut corners and keep your fingers crossed. The choice is obvious, isn't it?

- Krishna Balachandran
Director of Product Marketing
Low Power Verification Products
Synopsys Inc.





Comment on "Why voltage-aware verification strat..."
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
 
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

 

Go to top             Connect on Facebook      Follow us on Twitter      Follow us on Orkut

 
Back to Top