DesignWare DDR portfolio integrates DDR4 IP
The IP solution includes the DDR4 multi-PHY and Enhanced Universal DDR Memory Controller (uMCTL2) that connect through a commonly used DFI 3.1 interface.
The DDR4 IP supports all the key DDR4 features planned for the upcoming JEDEC standard. It claims to offer 13 per cent increase in raw bandwidth and up to 50 less overall latency. It is also said to include intelligent system monitoring and control to power down elements of the IP as determined by the system's traffic patterns, resulting in lower power use.
Also, real-time scheduling features in Synopsys' unique CAM-based DDR controller can optimise the scheduling of data read/write traffic from multiple hosts, maximising performance and minimising latency.
The DesignWare DDR4 multi-PHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4 is expected to be available in 4Q 12.
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