Cadence, TSMC build stronger ties in 16nm FinFET process tech
The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs—from design analysis through signoff—and will deliver the infrastructure necessary to enable ultra low-power, high-performance chips.
FinFETs help deliver the power, performance, and area (PPA) advantages that are needed to develop highly differentiated SoC designs at 16nm and smaller process technologies. Unlike a planar FET, the FinFET employs a vertical fin-like structure protruding from the substrate with the gate wrapping around the sides and top of the fin, thereby producing transistors with low leakage currents and fast switching performance. This extended Cadence-TSMC collaboration will produce the design infrastructure that chip designers need for accurate electrical characteristics and parasitic models required for advanced FinFET designs for mobile and enterprise applications.
"The FinFET device requires greater accuracy, from analysis through signoff, and that is why TSMC is teaming with Cadence on this project," said Suk Lee, TSMC senior director, design infrastructure marketing division. "This collaboration will enable designers to use the new process technology with confidence earlier than ever before, allowing our mutual customers to meet their power, performance and time-to-market goals."
"Producing the design infrastructure necessary for these types of complex, groundbreaking processes requires close collaboration between foundries and EDA technology innovators," said Chi-Ping Hsu, senior vice president, silicon realization group at Cadence. "In joining with TSMC, a leader in FinFET technology, Cadence brings unique technology innovations and expertise that will provide designers with the FinFET design capabilities they need to bring high-performance, power-efficient products to market."
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