Inc. has introduced what it describes as an innovative test technology
to cut the cost of testing silicon devices by delivering up to three times higher test compression and reducing the time required to test each silicon die. According to the company, the technology also uses fewer pins and higher-frequency on-chip design-for-test
(DFT) circuitry, enabling design teams to test several die in parallel and use the maximum performance of their tester equipment to achieve additional reduction in test time and cost.
Embedded in Synopsys' Design Compiler RTL synthesis and TetraMAX ATPG solutions, the test technology delivers faster test time and higher test quality without adversely impacting design goals and schedules, added the company.
Engineers are increasingly testing silicon parts in parallel and at faster frequencies while adding more tests. Synopsys' synthesis-based test technology uses an innovative method to efficiently stream compressed test data in and out of the DFT circuitry, significantly lowering the amount of data required to achieve high test quality. This method requires fewer test pins and enables silicon parts to operate at higher frequencies while in test mode. As a result, more die can be tested in parallel, and the time required to test each die is further reduced. To deliver superior quality of results and faster turnaround time, design teams implement the DFT for the technology with the Synopsys Galaxy Implementation Platform suite of tools, concurrently balancing design constraints by performing intelligent tradeoffs between speed, area, power, test and yield, stated Synopsys.