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Three firm bolster Accellera Systems Initiative

Posted: 31 Jul 2013  Print Version  Bookmark and Share

Keywords:STMicroelectronics  ARM  Cadence Design Systems 

STMicroelectronics, ARM and Cadence Design Systems Inc. have announced three contributions to the SystemC Language Working Group of the Accellera Systems Initiative. The firms said the collaboration will further increase model and tool interoperability for electronic system-level (ESL) design at the transaction-level.

The joint work includes new interfaces for interrupt modelling, which allow seamless integration of models from different companies; application programming interfaces for register introspection that enable tool interoperability to seamlessly display and update register values; and new approaches for memory-map modelling that improve users' productivity during debugging of virtual platforms for hardware/software multi-core systems.

The contributions consist of fully working application programming interfaces (API) and implementations, as well as documentation and examples, released under an Apache 2.0 open-source licence and available online at http://forums.accellera.org/files/.

"These new interfaces are crucial to strengthening the ESL ecosystem. As a step towards interoperability driven by ST, ARM and Cadence, these proposed standards dramatically reduce risks and efforts associated with the integration of virtual prototypes. Eliminating the need for adapters will increase virtual prototype simulation performances, enable sooner and faster hardware-software integration, and therefore improve product time-to-market," said Philippe Magarshack, EVP, design enablement and services, ST.

"The Accellera TLM 2 standard has been very important in enabling an ecosystem of models that can be integrated into SystemC virtual prototypes," said John Goodenough, VP of design technology and automation, ARM. "By addressing a key gap in the model-to-model interface and by enhancing tool integration, these proposed contributions further help in ensuring virtual prototypes can be predictably and consistently integrated."

The first technical proposal addresses the need for better interoperability among SystemC TLM models and proposes a standard interface to model interrupts and wires at the Transaction Level. This will enable seamless integration of models from different companies with standardised memory-mapped connections, further enhancing the growth of a market for third-party TLM models.

The second proposal defines a standard interface between models and tools to support register introspection, enabling tools to seamlessly display and update register values. This interface works in a mix of different user-defined register classes to support platforms integrating heterogeneous models from various model providers. This capability is a key enabler for integration and debug of embedded software on pre-silicon virtual prototypes.

The third proposal introduces an approach to reconstruct system memory maps as seen from initiators, enabling ESL tools to support hardware/software debug on complex virtual platforms, for which understanding of the memory maps is instrumental. It addresses the challenge that memory maps depend on the interconnection of models and as a result each system initiator might have its own view.

With these contributions, ST, ARM and Cadence expect the integration of SystemC models in virtual prototypes will be significantly improved for all users, enabling the models' quick and efficient deployment. In addition, standard interfaces between models and tools will extend hardware/software integration and debug capabilities using appropriate tools.

Within the Accellera Systems Initiative, ARM, Cadence and ST plan to work with other companies to refine and fully standardise these proposals.





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