Cadence: 'India offers great environment for Tempus'
Molina: Our main focus now is to ensure the success of the Tempus solution in the customers' hands.
EDA firm Cadence Design Systems Inc. recently announced the launch of its new signoff tool, Tempus. The new solution, which enables customers to shrink timing signoff closure and analysis for faster tape-out, compete against the "standard" and trusted tool 'PrimeTime' from Synopsys. Tempus is said to be up to 10X faster than competing solutions, and it also gets the backing of Texas Instruments as its first customer. In an exclusive interview with EE Times India's Arti Singh, Ruben Molina, Product Marketing Director – Signoff Solutions, Cadence Design Systems Inc., talks about Tempus and why India is an important market for the new static timing analysis (STA) tool.
EE Times India: Tell us more about the Tempus solution? What are the current challenges with signoff and how Cadence's Tempus solution addresses these issues?
Molina: The tool challenges today consist primarily of the time it takes to get through timing signoff closure due to increasing design sizes and timing views and, the ability to model waveform effects at the lower process nodes. Today's solutions for signoff timing closure fall short in their predictability of timing optimisation success because they are not integrated with the physical properties of the layout. The current tools on the market are also based on older architectures that were not optimised for multi-core processing or parallelized computation. In the area of waveform modelling, delay calculation tools have ignored many of the effects that impact waveform shape at the older nodes because the impacts were minimal. Starting at 28nm and continuing through 16nm, these effects have a dramatic effect on what input waveforms look like and therefore cannot be ignored during delay computation.
The Tempus solution solves all of these problems because of its innovative and up to date processing architecture, which leverages massively parallelized computation. The result is extremely fast runtimes by leveraging many CPUs to analyse the design, especially for complex designs. The Tempus solution is also physically aware which significantly improves timing optimisation predictability and success. Finally, as a signoff tool the Tempus solution needs to be as accurate as possible. In this regard the Tempus tool employs the latest in signal integrity and waveform modelling to ensure the upmost accuracy especially at 20nm and below. TSMC's certification of the Tempus solution at the 20nm node is a strong indication of how well the Tempus solution is able to model these effects.
Synopsys PrimeTime is seen as the biggest competition for the Cadence Tempus tool. How are you planning to take on the popularity of PrimeTime?
Our strategy for any tool is to provide an innovative solution that solves a customer's problems. We think we have those qualities in the Tempus solution.
What do you think would persuade people to switch from traditional, or let's say already established, solutions to the Tempus?
Runtime performance is the number one reason as long as accuracy is maintained. With massively parallelized computation, the Tempus solution can distribute the timing analysis problem across many compute resources where each compute resource may have many CPUs. In addition to our ability to scale with increasing number of CPUs, we have also made significant performance improvements in Path Based Analysis, which allows designers to reduce pessimism over a larger portion of their designs. This reduces time to fix false timing violations, minimises area and power. These benefits are not specific to large-scale designs. They apply to ALL designs of any technology.
The Tempus tool is a solution that easily scales to future technologies. Customers can adopt the Tempus solution knowing that it is a solution which is not out of date nor is it likely to be for a long time.
What kind of opportunities do you see in India for the new signoff solution?
India contains many of the largest IDMs and fabless semiconductor companies as well as a plethora of innovative start-up companies. Collectively these companies are pushing the limits on design sizes and advanced nodes. This is exactly the kind of design environment where innovative solutions like the Tempus solution are needed. We look forward to working with our customers in India.
Can you brief us about your collaboration with Texas Instruments? Other than TI, can you name few other customers for the Tempus solution?
TI is a very important and valued customer and we continue to partner with them pushing the limits of what our solutions can do. TSMC is another partner in which we have a close working relationship and work with to meet the demands of advanced process nodes. The fact that each was publicly visible in our rollout of the Tempus solution speaks volumes of our relationships with these leading edge companies.
How is Cadence planning to take its Tempus signoff solution further?
It's not enough to rest on the innovations rolled out in the Tempus solution. We must continue to look beyond the "next" generations of designs and anticipate the kinds of problems that advanced design houses will have in signoff. However our main focus now is to ensure the success of the Tempus solution in the customers' hands. Only through the success of our customers can we ultimately take the Tempus solution further in the future.
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