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28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST
Texas Instruments
Description
This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM loads. All inputs are SSTL_18, except the chip-select gate-enable (CSGateEN) and reset (RESET
Features
Member of the Texas Instruments Widebus+™ Family Pinout Optimizes DDR2 RDIMM PCB Layout 1-to-2 Outputs Supports Stacked DDR2 RDIMMs Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line Supports SSTL_18 Data Inputs Differential Clock (CK and CK
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