2 inputs, 1 output HDMI/DVI links: HDMI 1.3 receive & transmit compliant Four TMDS channels per link: Supports 250 Mbps - 2.25 Gbps data rates and beyond Supports 25 MHz - 225 MHz pixel clocks and beyond Fully buffered unidirectional inputs/outputs Globally-switchable 50 ? on-chip terminations Equalized inputs and pre-emphasized outputs Fully flexible input/output mapping Input terminations disabled for unselected inputs Three auxiliary channels per link: Buffered and switched DDC bus (SDA and SCL) DDC bus logic level translation (3.3 V, 5 V) Buffered CEC bus with integrated pull-up resistors (27 k?) Hot plug detect pulse low on channel switch Input/output capacitance isolation Output disable feature: Reduced power dissipation Output termination removal on TMDS channels Single-supply operation (3.3 V) Standards compatible: DVI, HDMI 1.3, HDCP, CEC Serial (I2C slave) control interface 56-pin 8 mm × 8 mm LFCSP Pb-free package