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5-43MHz DC- Balanced 24-Bit LVDS Serializer
National Semiconductor
Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS90UR241/124 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are randomized to the Deserializer without the need of REFCLK.
Features
• 5 MHz–43 MHz embedded clock and DC-Balanced 24:1 and 1:24 data transmission
• User defined pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10 meters shielded twisted-pair cable
• User selectable clock edge for parallel data on both Transmitter and Receiver
• Supports AC-coupling data transmission
• Individual power-down controls for both Transmitter and Receiver
• Embedded clock CDR (Clock and Data Recovery) on Receiver and no source of reference clock required
• All codes RDL (random data lock) to support live-pluggable applications
• LOCK output flag to ensure data integrity at Receiver side
• Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side
• Adjustable PTO (progressive turn-on) LVCMOS outputs on Receiver to minimize EMI and SSO effects
• @Speed BIST to validate LVDS transmission path
• All LVCMOS inputs and control pins have internal pulldown
• On-chip filters for PLLs on Transmitter and Receiver
• 48-pin TQFP package for Transmitter and 64-pin TQFP package for Receiver
• Pure CMOS .35 µm process
• Power supply range 3.3V ± 10%
• Temperature range –40°C to +105°C
• Greater than 8 kV HBM ESD structure
• Meets ISO 10605 ESD and AEC-Q100 compliance
• Backward compatible mode with DS90C241/DS90C124
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