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16 MHz - 40 MHz 10-Bit Bus LVDS Random Lock Deserializer with Embedded Clock Recovery
National Semiconductor
Description
The DS92LV1212A is an upgrade of the DS92LV1212. It maintains all of the features of the DS92LV1212. The DS92LV1212A is designed to be used with the DS92LV1021 Bus LVDS Serializer. The DS92LV1212A receives a Bus LVDS serial data stream and transforms it into a 10-bit wide parallel data bus and separate clock. The reduced cable, PCB trace count and connector size saves cost and makes PCB layout easier. Clock-to-data and data-to-data skews are eliminated since one input receives both clock and data bits serially. The powerdown pin is used to save power by reducing the supply current when the device is not in use. The Deserializer will establish lock to a synchronization pattern within specified lock times but it can also lock to a data stream without SYNC patterns.
Features
• Clock recovery without SYNC patterns-random lock
• Guaranteed transition every data transfer cycle
• Chipset (Tx + Rx) power consumption < 300mW (typ) @ 40MHz
• Single differential pair eliminates multi-channel skew
• 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock)
• 10-bit parallel interface for 1 byte data plus 2 control bits or UTOPIA I Interface
• Synchronization mode and LOCK indicator
• Flow-through pinout for easy PCB layout
• High impedance on receiver inputs when power is off
• Programmable edge trigger on clock
• Footprint compatible with DS92LV1210
• Small 28-lead SSOP package-MSA
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