TMS470R1B768 (Rev. A)
Texas Instruments
Description
The TMS470R1B768(2) device is a member of the Texas Instruments (TI) TMS470R1x family of general-purpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The B768 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1B768 utilizes the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.High-end embedded control applications demand more performance from their controllers while maintaining low costs. The B768 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.The B768 device contains the following: ARM7TDMI 16/32-Bit RISC CPUTMS470R1x system module (SYS) with 470+ enhancements [including an interrupt expansion module (IEM) and a 16-channel direct-memory access (DMA) controller]768K-byte flash48K-byte SRAMZero-pin phase-locked loop (ZPLL) clock moduleAnalog watchdog (AWD) timerReal-time interrupt (RTI) moduleFive serial peripheral interface (SPI) modulesTwo serial communications interface (SCI) modulesThree high-end CAN controller (HECC) modules10-bit multi-buffered analog-to-digital converter (MibADC) with 16 input channelsHigh-end timer (HET) controlling 32 I/OsExternal clock prescale (ECP) moduleUp to 86 I/O pins and 1 input-only pinThe functions performed by the 470+ system module (SYS) include: Address decodingMemory protectionMemory and peripherals bus supervisionReset and abort exception managementExpanded interrupt capability with prioritization for all internal interrupt sourcesDevice clock controlDirect-memory access (DMA) and controlParallel signature analysis (PSA) This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189). For a more detailed functional description of the IEM module, see the TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211). And for a more detailed functional description of the DMA module, see the TMS470R1x Direct-Memory Access (DMA) Controller Reference Guide (literature number SPNU210). The B768 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. ......
Features
High-Performance Static CMOS Technology TMS470R1x 16/32-Bit RISC Core (ARM7TDM) 60-MHz (Pipeline Mode) Independent 16/32-Bit Instruction Set Open Architecture With Third-Party Support Built-In Debug Module Utilizes Big-Endian Format Integrated Memory 768K-Byte Program Flash 3 Banks With 18 Contiguous Sectors Internal State Machine for Programming and Erase 48K-Byte Static RAM (SRAM) 15 Dedicated GIO Pins,1 Input-Only GIO Pin, and 71 Additional Peripheral I/Os Operating Features Core Supply Voltage (VCC): 1.81-2.05 V I/O Supply Voltage (VCCIO): 3.0-3.6 V Low-Power Modes: STANDBY and HALT Extended Industrial Temperature Range 470+ System Module 32-Bit Address Space Decoding Bus Supervision for Memory and Peripherals Analog Watchdog (AWD) Timer Real-Time Interrupt (RTI) System Integrity and Failure Detection Interrupt Expansion Module (IEM) Direct Memory Access (DMA) Controller 32 Control Packets and 16 Channels Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler Multiply-by-4 or -8 Internal ZPLL Option ZPLL Bypass Mode Ten Communication Interfaces: Five Serial Peripheral Interfaces (SPIs) 255 Programmable Baud Rates Two Serial Communications Interfaces (SCIs) 224 Selectable Baud Rates Asynchronous/Isosynchronous Modes Three High-End CAN Controllers (HECCs) 32-Mailbox Capacity Each Fully Compliant With CAN Protocol, Version 2.0B High-End Timer (HET) 32 Programmable I/O Channels: 24 High-Resolution Pins 8 Standard-Resolution Pins High-Resolution Share Feature (XOR) High-End Timer RAM 128-Instruction Capacity 16-Channel 10-Bit Multi-Buffered ADC (MibADC) 256-Word FIFO Buffer Single- or Continuous-Conversion Modes 1.55 µs Minimum Sample and Conversion Time Calibration Mode and Self-Test Features Eight External Interrupts Flexible Interrupt Handling External Clock Prescale (ECP) Module Programmable Low-Frequency External Clock (CLK) On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1(1) (JTAG) Test-Access Port 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix) (1)The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device. (2) Throughout the remainder of this document, TMS470R1B768 shall be referred to as either the full device name or B768.ARM7TDM is a trademark of Advanced RISC Machines Limited (ARM). All other trademarks are the property of their respective owners.
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