Each TPS2343 contains main supply power control, auxiliary supply power control, power FETs for 12-V, -12-V and auxiliary 3.3-V supplies, VIO control, and digital control for two slots. The main power control circuits start with all supplies off and all outputs are held off until PGOOD is asserted, indicating that system supplies are valid. Then, when power enable is asserted, the control circuit applies constant current to the gates of the power FETs, allowing each FET to ramp load voltage linearly. Each supply can be programmed for a desired ramp rate by selecting the appropriate gate capacitor. The TPS2343 monitors load current and regulates peak current to prevent disturbances to the system power rails. If load current remains regulated for longer than 5 ms, that slot is latched off. Logic inputs to the TPS2343 access all functions of the TPS2343. All status information from the TPS2343 is available on logic outputs. Auxiliary power control circuits switch, ramp, and monitor 3.3-V auxiliary power to each slot and control data switches that connect slot power management event (PME) outputs to the main PME bus after auxiliary supply is ramped. PME is disconnected when a board is turned off or a fault occurs on the board’s auxiliary power. A fault on auxiliary power also shuts off main power to that board. VIO control consists of gate drivers to select between 3.3 V and 1.5 V in response to command and current limiting circuitry to shut down a slot in the event of over current. Each TPS2343 contains power FETs for 12 V, -12 V, and auxiliary 3.3 V for two slots. These power FETs are short-circuit protected, slew rate controlled, and over-temperature protected. The TPS2343 includes novel current limiting circuitry that limits instantaneous peak current and only shuts off the slot if the current remains out of spec for an extended time.