Fabricated in 0.5 micron CMOS technology, the GC2011A chip is a general purpose digital filter chip with 32 multiply-add filter cells. The chip operates at rates up to 106 MHz. The input data size is 12 bits and the coefficient data size is 14 bits. The output data size is 8, 10, 12, 14, 16, 20 or 24 bits. The 32 multiply-add cells can be arranged as a 32 tap arbitrary phase filter or a 64 tap linear phase filter with even or odd symmetry. Decimation and interpolation modes double or quadruple the number of taps in the filter. Two input ports allow the 32 filter cells to be shared between two data paths in order to process two signals or to process complex data. Each path becomes a 16 tap arbitrary phase filter, a 32 tap symmetric filter, a 64 tap decimate by 2 filter or a 128 tap decimate by 4 filter. Coefficient double buffering and clock synchronization logic permits the user to switch between coefficient sets without causing any undesirable transients in the filter?s operation. Complex coefficients can be handled using an add/subtract cell which combines the two data paths. A complex data by complex coefficient filter requires two chips, one for the I output and one for the Q output. The number of complex taps varies from 16 to 128 depending upon the symmetry and desired I/O rate. The input data rate can be equal to the clock rate, half the clock rate or a quarter of the clock rate. The effective number of taps doubles for half rate data and quadruples for quarter rate data. The input data rate can be extended to 212 MHz if two chips are used. With two chips the filter size is 32 taps arbitrary phase or 64 taps linear phase. If decimation by two is desired, then only one chip is required and the filter size is 64 taps. A single chip can be used to convert data between real and complex formats. When converting from real to complex the chip mixes the signal down by FS/4 and lowpass filters the results. To convert from complex to real the chip interpolates the signal by two, mixes it up by FS/4 and outputs the real part of the result. The two 12 bit data paths can be used to process 24 bit input data by filtering the upper 12 bits in one path and the lower 12 bits in the other. A 12 bit shift and add circuit merges the results into a 24 bit output. The chip includes a snapshot memory which can capture blocks of input or output data. The size of the snapshot can be programmed to be two 128 sample by 16 bit snapshots, two 256 sample by 8 bit snapshots, one 256 sample by 16 bit snapshot, or one 512 sample by 8 bit snapshot. These samples can be read by an external processor and used for adaptive updates of the filter coefficients. The internal data precision is 32 bits, sufficient to preserve the full multiplier products and to prevent overflow in the filter?s adder tree. The 32 bit results are passed through a gain circuit before they are rounded to 8, 10, 12, 14, or 16 bits. The gain circuit can adjust the signal?s amplitude over a 96 dB range ......