Electronics Design & EDA Tools [EDA/IP/Application Notes][Page 12]

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Application Notes (Sorted By Date)

Synthesizing LSS designs with Synopsys design compiler (25/04/01)
Boundary scan and internal scan (23/04/01)
Using NAND tree test circuits for input parametric testing (23/04/01)
Guidelines for supplying test vector simulations (23/04/01)
Clocking at AMI (23/04/01)

Varactor SPICE models for RF VCO applications (19/04/01)
Data generation and configuration for Spartan series FPGAs (12/04/01)
Programming interrupts for DOS-based data acquisition on 80x86-based computers (30/03/01)
Understanding the Warp report file for Ultra37000-devices (30/03/01)
Importing a Warp post-fit netlist into Mentor Graphics' ModelSim (30/03/01)

Targeting Cypress PLDs from the Synopsys FPGA Express environment (29/03/01)
Targeting Cypress ISR CPLDs with Synplify 6.0 (28/03/01)
An introduction to active-HDL Sim (28/03/01)
Software considerations for the VIC64 (28/03/01)
Targeting Cypress PLDs from the Leonardo Spectrum Environment (26/03/01)

Using IEEE 1149.1 boundary scan (JTAG) with Cypress Ultra37000 CPLDs (23/03/01)
Using hierarchy in VHDL design (22/03/01)
An Introduction to active-HDL FSM (22/03/01)
FIFO Dipstick using Warp2 VHDL and the CY7C371 (21/03/01)
ISR programming using an embedded processor with Jam (21/03/01)

Method to instantiate and use a core in Warp Enterprise/Professional (21/03/01)
Method to instantiate and use a core in Warp with Cypress CPLDs (20/03/01)
Getting started converting .ABL files to VHDL (20/03/01)
Method to instantiate and use a core in Synplify (20/03/01)
Abel-HDL vs. IEEE-1076 VHDL (20/03/01)

Targeting Cypress PLDs from the Cadence environment (20/03/01)
Method to instantiate and use a core in LeonardoSpectrum (20/03/01)
An introduction to in-system reprogramming (ISR) with the Ultra37000 (19/03/01)
ECLinPS circuit performance at non-standard VIH levels (06/12/00)
MC10X1189 I/O SPICE modeling kit (06/12/00)

MC10/100H600 translator family I/O SPICE modeling kit (06/12/00)
FACT I/O model kit (05/12/00)
Fanout (04/12/00)
Smart_route (04/12/00)
Stub length (04/12/00)

Testpoints (04/12/00)
Did file editing (04/12/00)
Tandem features (01/12/00)
Area fills in 7.1 (01/12/00)
Color and key functions (01/12/00)

BGA (Ball Grid Array) (30/11/00)
Using DPPs in the C16x (29/11/00)
Classes and sections in C16x (29/11/00)
Memory models in C16x (29/11/00)
In-system FLASH programming with C16x/ST10 (29/11/00)

Using the ST10 MAC unit (On the ST10-272) with Keil C166 development tools (29/11/00)
Quiet FCT logic advantages: Replacement for ABT logic (28/11/00)
FCT vs. ABT logic comparison (28/11/00)
Solutions to current high-speed board design (28/11/00)

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