Switching Regulator Power Loss
Efficiency can be a misleading number for comparison of switching regulators. Efficiency number can be manipulated by input and output voltage, while power loss is more tightly tied to the actual circuit --- Click here to watch the video and learn why.
Efficiency can be a misleading number for comparison of switching regulators. Efficiency number can be manipulated by input and output voltage, while power loss is more tightly tied to the actual circuit --- Click here to watch the video and learn why.
Technical Archives (Sorted By Date)
- Create sounds using analogue electronics (Part 6) (04/04/12)
- Spatial audio generation from portable devices (Part 2) (30/03/12)
- Create sounds using analogue electronics (Part 5) (03/02/12)
- Spatial audio generation from portable devices (Part 1) (19/01/12)
- Create sounds using analogue electronics (Part 4) (10/01/12)
- A tutorial on digital signalling (Part 3) (19/12/11)
- Create sounds using analogue electronics (Part 3) (06/12/11)
- Managing different clock frequencies of audio codecs (02/12/11)
- Know the EMI sources in touchscreens (01/12/11)
- A tutorial on digital signalling (Part 2) (24/11/11)
- A tutorial on digital signalling (Part 1) (22/11/11)
- A tutorial on radio link (Part 4) (21/11/11)
- Designing improved DC/DC regulator using FPGA (18/11/11)
- Learn about root mean square (15/11/11)
- Create sounds using analogue electronics (Part 2) (08/11/11)
- Boost DAC integral non-linearity through gain correction (25/10/11)
- Trade-offs of multi-gigabit data link aggregation (17/10/11)
- Designing software-defined radio (Part 1) (13/10/11)
- Addressing traditional radio design issues (10/10/11)
- Create sounds using analogue electronics (Part 1) (04/10/11)
- Cut EMI in digital systems with spread spectrum clock generators (Part 2) (05/09/11)
- Cut EMI in digital systems with spread spectrum clock generators (Part 1) (01/09/11)
- Important principles for practical analogue BIST (01/08/11)
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3D IC opens new doors for the wireless market
(20/06/11)
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Addressing challenges in PWM generator validation
(23/05/11)
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Noise optimisation in sensor signal-conditioning ICs (Part 2)
(09/05/11)
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Noise optimisation in sensor signal-conditioning ICs (Part 1b)
(18/04/11)
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Signal Chain Basics: Basics of clock jitter specs in high-speed links (Part 1)
(18/04/11)
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Differential gain and phase: Why measure what we can't see?
(11/04/11)
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Correlating to good effect
(07/03/11)
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Eliminate signal degradation in wireless network
(07/03/11)
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ADCs offer high sample rates with low power
(17/01/11)
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Employing averaging filter
(20/12/10)
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Implementing analogue video interfaces (Part 2)
(06/07/10)
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Implementing analogue video interfaces (Part 1)
(02/07/10)
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What's a clock jitter?
(18/05/10)
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Using reference designs in implementing low, high frequency ADCs
(08/04/10)
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Exploring the types of combinational loops
(18/03/10)
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Providing superior Internet video QoE
(06/01/10)
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Enabling 3D data capture
(23/12/09)
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Ease cross-domain signal protection for mixed-signal SoCs
(11/12/09)
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How to improve system time synchronisation accuracy
(03/12/09)
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Guidelines for selecting op amps for your ADC
(27/11/09)
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Handling the challenges of interleaving high-speed ADCs
(19/11/09)
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Analogue integration made possible with mixed-signal MCUs
(12/11/09)
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Simplifying sensor signal conditioning (Part 2)
(30/10/09)
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Simplifying sensor signal conditioning (Part 1)
(29/10/09)
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Improve DSP performance with on-chip FFT
(09/10/09)
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Transmit audio, video data efficiently with MOST
(22/09/09)
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Control analogue output from CPLD with PWM
(08/04/09)
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