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| 2011-12-13 | Ref design saves power on Bluetooth-based HIDs Ref design saves power on Bluetooth-based HIDs |
| 2011-02-01 | Ease production at 65nm with DFM Ease production at 65nm with DFM |
| 2010-12-09 | SMIC adopts Cadence tools for 65nm design SMIC adopts Cadence tools for 65nm design |
| 2010-11-24 | TSMC qualifies Synopsys' IC Validator TSMC's qualification of Synopsys IC Validator offers the advantages of the in-design flow to the broad range of design teams utilising TSMC's 40nm and 65nm process technologies. |
| 2010-09-21 | SMIC adopts Cadence range for design solutions SMIC adopts Cadence range for design solutions |
| 2010-08-27 | Physical verification solutions aid 65nm transition Physical verification solutions aid 65nm transition |
| 2009-05-28 | Exar to use Synopsys platforms for 65nm designs Exar to use Synopsys platforms for 65nm designs |
| 2009-03-26 | TSMC, Ciranova team up on advanced design kits TSMC, Ciranova team up on advanced design kits |
| 2009-03-18 | Broadcom platform enables low-cost IP phones Broadcom has announced a scalable IP communications design platform featuring 65nm IP communications processors. |
| 2009-01-02 | Sub-100nm tech brings EDA opportunities Know the challenges in sub-100nm design and the tools that could improve designer's productivity. |
| 2008-11-17 | New techs address 40nm, 65nm design issues New techs address 40nm, 65nm design issues |
| 2008-10-23 | Multi-Vdd methodology reduces power at 65nm Multi-Vdd methodology reduces power at 65nm |
| 2008-06-24 | VLSI industry focused on 1-10 million-gate designs VLSI design services provided by companies in India brought in Rs.3,041.60 crore ($760 million) last year, according to ISA. |
| 2008-06-16 | UMC takes a step away 450mm wafers UMC has outlined its process roadmap and disclosed several alliances with the EDA community at the DAC. |
| 2008-06-10 | MediaTek adopts IC Compiler for 65nm SoC designs MediaTek adopts IC Compiler for 65nm SoC designs |
| 2008-01-31 | Toshiba deploys Cadence ultraslim simulator Cadence has announced that Toshiba has deployed its Virtuoso UltraSim full-chip simulator for reliability analysis at 65nm and below to help ensure high performance and improve yield and quality of devices. |
| 2007-09-24 | Magma, UMC team release verification, DFM tools for 65nm Magma, UMC team release verification, DFM tools for 65nm |
| 2007-09-24 | Firms address 65nm FPGA design verification Firms address 65nm FPGA design verification |
| 2007-07-18 | Infineon licenses MIPS32 74K core Infineon Technologies has licensed MIPS Technologies' MIPS32 74K core for its next- gen IC designs. |
| 2007-07-12 | Advanced design flow addresses 65nm DFM issues Advanced design flow addresses 65nm DFM issues |
| 2007-06-28 | TSMC, Cadence partners on 65nm wireless design flow TSMC, Cadence partners on 65nm wireless design flow |
| 2007-06-18 | Industry tackles approach to DFM, DFY issues Experts from chip, EDA and foundry companies ask whether it's better to deal with DFM and DFY issues at tape-out or minister to the design starting at the register transfer level. |
| 2007-06-16 | Updating DFT strategies for nanometre designs As the industry races toward 90nm and 65nm nodes, a "complete" solution with advanced test patterns and fault models is needed to improve defect detection. |
| 2007-05-08 | Start-up aims to become "TSMC of design Start-up aims to become "TSMC of design |
| 2007-04-25 | Common Platform partners roll 65nm reference flow Common Platform partners roll 65nm reference flow |
| 2007-04-18 | Implement low-power 65nm FPGA designs Implement low-power 65nm FPGA designs |
| 2007-04-18 | Apache low-power solution addresses 65nm, 45nm Apache low-power solution addresses 65nm, 45nm |
| 2007-03-23 | Conquer loss, create high-yielding designs This article discusses the three most important yield-loss mechanisms in 65nm designs, and proposed methods for mitigating yield loss without severe impact on design schedules. Using tools that are both powerful and well-integrated, design and layout engineers can create high-yielding designs while meeting design specifications and demanding schedules. |
| 2007-03-15 | Cadence solution enables Taiwan's first 65nm IC design Cadence solution enables Taiwan's first 65nm IC design |
| 2007-03-09 | Fujitsu standardises on Synopsys solutions for 65nm sign-off Fujitsu standardises on Synopsys solutions for 65nm sign-off |
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