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| 2012-01-25 | S/w release targets safety-critical apps Aldec adds documentation support for ALINT 2012.01, a design rule checking app targeted at safety-critical industries such as DO-254 for avionics, IEC 61508/61513 for nuclear and ISO 26262 for automotive. |
| 2010-06-16 | Employing clock gating in ASIC, FPGA designs Employing clock gating in ASIC, FPGA designs |
| 2009-11-27 | Processor cores support 96 user-defined instructions The processor cores based on EnSilica's eSi-RISC scalable processor architecture support both 16 and 32bit configurations suitable for a number of ASIC and FPGA designs. |
| 2009-09-22 | Execs tackle ASIC, FPGA design challenges Execs tackle ASIC, FPGA design challenges |
| 2009-03-12 | IP cores aim SoC, ASIC, FPGA designs IP cores aim SoC, ASIC, FPGA designs |
| 2008-11-19 | Aldec unveils Riviera-PRO 2008.10 The Riviera-PRO 2008.10 is an HDL mixed-language simulator for multi-million gate ASIC and FPGA designs. |
| 2008-11-05 | Altera enhances Quartus II software Altera has unveiled Quartus II software version 8.1 for CPLD, FPGA, and HardCopy ASIC designs. |
| 2006-09-17 | Billion-transistor full-custom designs Billion-transistor full-custom designs |
| 2008-06-16 | Implement an FPGA ASIC prototype Implement an FPGA ASIC prototype |
| 2008-06-23 | Freescale reveals 'first' multi-standard accelerator Freescale debuts a chip that is said to be the industry's first multi-standard base band accelerator. |
| 2007-11-15 | Altera, Synopsys team to offer Nios II for ASIC designs Altera, Synopsys team to offer Nios II for ASIC designs |
| 2007-11-01 | Devt tool provides seamless migration to structured ASICs Based on Altera's Stratix II FPGAs, TrellisWare has launched new RapidFire development board that enables fast prototyping and testing of complex PHY designs.. |
| 2007-02-01 | Tundra division rolls out Interlaken IP core Silicon Logic Engineering Inc. (SLE) has developed a licensable Interlaken protocol IP core for use in ASIC or FPGA designs. SLE's Interlaken IP core is scalable, with early versions providing from 10Gbps to 60+Gbps bandwidth across the interface. |
| 2006-01-01 | Debug OCP designs with on-chip instrumentation Debug OCP designs with on-chip instrumentation |
| 2001-01-01 | EDA platform benchmark: The desktop FPGA design flow EDA platform benchmark: The desktop FPGA design flow |
| 2004-11-01 | FPGA co-processors optimize car infotainment, telematics FPGA co-processors optimize car infotainment, telematics |
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