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| 2012-03-14 | Accellera releases SystemC AMS 2.0 standard draft Accellera releases SystemC AMS 2.0 standard draft |
| 2012-01-25 | How formal MDV can take out IP integration uncertainty Find out how the formal metric-driven verification methodology and technologies can eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics. |
| 2011-12-07 | Accellera, OSCI merger approved Accellera, OSCI merger approved |
| 2011-05-02 | Accellera pushes for IP tagging standard Accellera pushes for IP tagging standard |
| 2011-02-01 | Co-emulation modelling verification standard revised Accellera, an EDA standards organisation has revised its verification standard with a version 2.1 of its Standard Co-Emulation Modelling Interface (SCE-MI) specification approved by its board of directors. |
| 2010-12-23 | Free IEEE 1685 IP reuse standard gets high traffic The IEEE 1685 standard programme sponsor, Accellera says its standard for IP reuse has been downloaded more than 1,200 times in the past six months since it first became available in June. |
| 2009-06-16 | Accellera merges with The Spirit Consortium Accellera merges with The Spirit Consortium |
| 2008-08-26 | Standard improves AMS design Accellera announced that its Board of Directors and Technical Committee members approved Verilog-AMS 2.3. |
| 2008-02-16 | VLSI Conference panel discusses EDA standards The panel discussion on "Standards in EDA" at the 2008 VLSI Design Conference had representatives from Accellera, IEEE, Si2 Consortium, AMS Committee and VSIA, agreeing that the Indian engineering community is gradually becoming a part of the standardisation process. |
| 2008-01-24 | Trio offers UPF-based low-power EDA tools Magma, Mentor and Synopsys have developed Accellera?s UPF 1.0 standard-based EDA tools with enhanced key low-power capabilities. |
| 2007-04-02 | Synopsys rolls design platform supporting UPF 1.0 Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format version 1.0 in its IC verification and implementation products in the second half of 2007. |
| 2007-02-21 | SystemVerilog fails to deliver on design SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support. |
| 2007-02-02 | Accellera launches UCI to define verification metrics Accellera launches UCI to define verification metrics |
| 2006-11-16 | Revised VHDL spec boosts IP security The Accellera standards organisation has approved a revised version of the VHDL specification, marking a huge step forward for the design language. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for IP encryption. |
| 2006-11-10 | Atrenta donates low power SGDC format to Accellera Atrenta donates low power SGDC format to Accellera |
| 2006-09-21 | Synopsys donates power management tech to EDA org Synopsys Inc. has donated power management technology to Accellera. The donation includes power management commands, SystemVerilog constructs, VHDL constructs and the Switching Activity Interchange Format. |
| 2006-07-26 | Accellera approves new VHDL standard Accellera approves new VHDL standard |
| 2005-08-29 | Accellera approves open verification library standard Accellera approves open verification library standard |
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