What are CPLDs?
| A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. It is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections. |
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| 2010-04-08 | Using reference designs in implementing low, high frequency ADCs Designers of digital systems are familiar with implementing the "leftovers" of their digital design by using FPGAs and CPLDs to glue together various processors, memories and standard function components on their PCB. |
| 2009-03-30 | Cut power in CPLD designs Know how power supply cycling can help to achieve low power consumption in their CPLD designs. |
| 2009-02-17 | Achieve zero standby current in CPLDs Achieve zero standby current in CPLDs |
| 2009-02-05 | Quartus II software upgraded The 9.0 version includes full support for Altera's portfolio of transceiver FPGAs and HardCopy ASICs. |
| 2008-12-16 | CPLDs tout small form factor CPLDs tout small form factor |
| 2008-11-25 | Manage power in FPGAs using CPLDs Manage power in FPGAs using CPLDs |
| 2008-11-19 | SMBus/I2C-compatible port expander Design a port expander that fits into CoolRunner-II XC2C32A—a port expander that is SMBus and I2C compatible. |
| 2008-11-17 | Quick start guide for MSP430x5xx Read about the features and benefits of I/O cells provided by Xilinx CoolRunner XPLA CPLDs. |
| 2008-11-17 | XPLA3 I/O cells Read about the features and benefits of I/O cells provided by Xilinx CoolRunner XPLA CPLDs. |
| 2008-11-12 | J Drive: ISC for IEEE Standard 1532 devices The J Drive programming engine offers direct in-system configuration support for IEEE Standard 1532 PLD. |
| 2006-09-20 | I/O gating versus sleep modes Here are the differences between CPLDs with an I/O gating feature, and the "sleep modes" used by FPGAs. |
| 2008-09-22 | Zero-power CPLDs enable low-power portable apps Zero-power CPLDs enable low-power portable apps |
| 2006-09-26 | Using CPLDs to manage power consumption in portables Using CPLDs to manage power consumption in portables |
| 2008-06-25 | Altera CPLDs travel to Shenzhen Altera CPLDs travel to Shenzhen |
| 2002-06-28 | Low power design with CoolRunner-II CPLDs Low power design with CoolRunner-II CPLDs |
| 2003-11-01 | The future of programmable logic Before long, platform FPGAs containing fixed or configurable processors and custom hardware will dominate the field of hardware design. By then, hardware/software codesign will be the norm. |
| 2006-02-02 | Program flash memory with parallel flash loaders and CPLDs Program flash memory with parallel flash loaders and CPLDs |
| 2008-01-08 | Altera unveils zero-power CPLDs for portable apps Altera unveils zero-power CPLDs for portable apps |
| 2007-11-16 | PLDs ease time-to-market pressures Today's devices provide the advantages of both an FPGA and a CPLD with a non-volatile, low-cost, instant-on high performance logic solution for applications that have traditionally used CPLDs. |
| 2007-03-06 | Micrel expands MIC68000 LDO family Micrel Inc. has introduced the 4A MIC68400, the latest addition to its MIC68000 family of LDOs designed specifically for powering FPGA, CPLDs, DSPs and MCUs. |
| 2006-10-12 | Toshiba selects Altera's CPLDs for its PMPs Toshiba selects Altera's CPLDs for its PMPs |
| 2006-07-20 | Macgraigor's boundary-scan tool eases FPGA, CPLD programming For programming FPGAs, CPLDs and other devices, Macraigor Systems LLC has announced the availability of J-SCAN Version 2.1 high-speed boundary-scan debug and programming tool. |
| 2001-03-19 | FLASH370i 5V to 12V dc-dc converter solutions This application note provides various solutions for the 12V super-voltage requirement for Cypress Semiconductor's Flash-based In-System Reprogrammable CPLDs in designs that do not already include a source for 12V. |
| 2001-03-26 | Power estimation and thermal management for Cypress CPLDs Power estimation and thermal management for Cypress CPLDs |
| 2004-12-10 | Configuring Xilinx FPGAs with SPI flash memories using CoolRunner-II CPLDs Configuring Xilinx FPGAs with SPI flash memories using CoolRunner-II CPLDs |
| 2001-03-21 | Understanding bus-hold: A feature of Cypress CPLDs Understanding bus-hold: A feature of Cypress CPLDs |
| 2001-03-19 | An introduction to in-system reprogramming (ISR) with the Ultra37000 This application note provides an introduction to Cypress Semiconductor's Ultra37000 family of In-System Reprogrammable (ISR) CPLDs. |
| 2001-03-22 | Using heat sinks with larger CPLDs Using heat sinks with larger CPLDs |
| 2002-12-06 | Benefits and advantages of SpeedLocking This application note discusses the benefits and advantages of using the SpeedLocked timing model in CPLDs. |
| 2001-03-30 | Understanding the Warp report file for Ultra37000-devices This application note provides a comprehensive description of the report file generated by the Warp HDL synthesis tool for the Ultra37000 CPLDs. |
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