What is DDR memory?
| Double Data Rate is a type of memory IC used in computers. Memory or storage medium is a device that where data can be held. DDR SDRAM (synchronous dynamic random access memory) is a type of memory widely used in computers. |
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| 2012-01-19 | Computer-on-module features 10/100Mb/s Ethernet Strategic Test's TX-28S computer-on-module features a 454MHz i.MX283 processor coupled with 64MB DDR SDRAM, 128MB NAND flash memory and a 200-pin SODIMM connector. |
| 2011-11-25 | Power tip: How to power DDR memory Power tip: How to power DDR memory |
| 2011-08-12 | Switching regulator supports all DDR standards Switching regulator supports all DDR standards |
| 2011-07-12 | ...177;6A switching regulator targets DDR termination ...177;6A switching regulator targets DDR termination |
| 2011-05-16 | MLC NAND chip packs 64Gb, DDR 2 interface MLC NAND chip packs 64Gb, DDR 2 interface |
| 2011-04-15 | DDR4 IP solution with optimised integration debuts Cadence team debuts a DDR4 IP solution and integration environment that claims to speed integration, reduce cost and ensure design manufacturability. |
| 2010-12-23 | 65nm SRAMs reduce power consumption up to 50% Cypress unveils its high-density QDRII+ SRAM portfolio with 65nm 36Mbit and 18Mbit devices offering reduced power consumption up to 50 per cent compared with 90nm SRAMs. |
| 2010-08-03 | Motherboard for 45nm processor uses dual channel mem Gigabyte Technology reveals the GA-G41M-Combo motherboard for the 45nm Intel multi-core processor that supports both DDR2 and DDR3 RAM. |
| 2010-07-28 | Samsung,Toshiba team on DDR 2.0 NAND Samsung,Toshiba team on DDR 2.0 NAND |
| 2010-06-07 | Overcome debugging challenges in DDR memory Overcome debugging challenges in DDR memory |
| 2010-05-28 | Cadence, IBM team on high performance IPs Cadence Design Systems, Inc. and IBM have signed an agreement to develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nanometer silicon-on-insulator. |
| 2010-05-10 | Buck regulator enables user-programmable frequency Linear Technology debuts the LTC3615, a synchronous buck regulator that operates from an input voltage of 2.25V to 5.5V, making it suitable for single-cell Li-ion applications as well as 3.3V and 5V intermediate bus systems. |
| 2010-05-10 | Configuring the SPEAr600 multi-port memory controller (MPMC) for external DDR SDRAM Configuring the SPEAr600 multi-port memory controller (MPMC) for external DDR SDRAM |
| 2010-04-27 | Interfacing DDR memories with the i.MX31 Interfacing DDR memories with the i.MX31 |
| 2010-04-13 | Power controller simplifies EMI filtering designs Exar Corp. has expanded its range of low-voltage, step-down controllers specifically targeted at DDR memory power architectures. |
| 2010-02-17 | PowerQUICC and QorIQ DDR3 SDRAM controller register setting considerations This application note expands on the description of the DDR3 memory controller programmable registers in the PowerQUICC and QorIQ processor reference manuals. |
| 2010-02-15 | Hardware and layout design considerations for DDR3 SDRAM memory interfaces Hardware and layout design considerations for DDR3 SDRAM memory interfaces |
| 2009-10-16 | DDR SDRAM shortage to last until Q1 10 DDR SDRAM shortage to last until Q1 10 |
| 2009-09-03 | DDR interleaving for PowerQUICC and QorIQ processors DDR interleaving for PowerQUICC and QorIQ processors |
| 2009-07-08 | Guide to LatticeSC/M DDR/DDR2 SDRAM memory interface Guide to LatticeSC/M DDR/DDR2 SDRAM memory interface |
| 2009-05-28 | Guide to using LatticeECP3 I/O interface Know how to use the capabilities of the LatticeECP3 devices to implement high-speed generic DDR interface, and the DDR, DDR2 and DDR3 memory interfaces. |
| 2009-04-14 | DDR memory power supply with buck converter DDR memory power supply with buck converter |
| 2008-10-08 | Evaluating memory system power for DDR3 Evaluating memory system power for DDR3 |
| 2008-08-19 | DDR IP portfolio targets SoC designs DDR IP portfolio targets SoC designs |
| 2008-08-08 | Regulator provides ultrafast transient response TI has launched a DDR regulator that suits all power management requirements for DDR, DDR2, DDR3 and DDR4 low-power memory termination. |
| 2008-08-04 | DDR2 PCB design: get it right the first time DDR2 is an evolutionary improvement over its predecessor, DDR, and is the next memory standard, as defined by Joint Electronic Device Engineering Council document JESD79-2E. Designers must completely comprehend the interface before doing layout so that they can create the boards "right the first time." |
| 2008-06-27 | PMIC backs up DDR battery PMIC backs up DDR battery |
| 2008-04-29 | DRAM controller ups efficiency by 20% Virage Logic has announced a DDR memory controller that can boost efficiency by 20 per cent while still maintaining low-power. |
| 2008-04-25 | Rambus joins Spansion on next-gen flash Rambus and Spansion have joined forces for DDR engineering and next-gen flash memory development. |
| 2008-02-16 | Selecting DDR memory power supply ICs Selecting DDR memory power supply ICs |
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