What is DDR memory?
| Double Data Rate is a type of memory IC used in computers. Memory or storage medium is a device that where data can be held. DDR SDRAM (synchronous dynamic random access memory) is a type of memory widely used in computers. |
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| 2012-03-29 | Peek inside the third-gen iPad Here's a photo essay that reveals the components of the latest iPad. |
| 2012-01-19 | Computer-on-module features 10/100Mb/s Ethernet Strategic Test's TX-28S computer-on-module features a 454MHz i.MX283 processor coupled with 64MB DDR SDRAM, 128MB NAND flash memory and a 200-pin SODIMM connector. |
| 2011-11-25 | Power tip: How to power DDR memory Power tip: How to power DDR memory |
| 2011-08-18 | Logic analyzer claims speed of 4Gb/s on 68 channels Agilent unveils the AXIe-based U4154A that offers capture speed of 4Gb/s on 68 channels and 2.5Gb/s on 136 channels and the ability to capture data on openings as small as 100ps by 100mV. |
| 2011-08-12 | Switching regulator supports all DDR standards Switching regulator supports all DDR standards |
| 2011-07-12 | ...177;6A switching regulator targets DDR termination ...177;6A switching regulator targets DDR termination |
| 2011-05-17 | NAND Flash controller complies with ONFI 3.0 Arasan's NAND Flash Controllers comply with the ONFI 3.0 specification while supporting fast transfer modes up to 400MTS with differential signalling on clock and data, and double data-rate transfers (DDR). |
| 2011-05-16 | MLC NAND chip packs 64Gb, DDR 2 interface MLC NAND chip packs 64Gb, DDR 2 interface |
| 2011-04-15 | DDR4 IP solution with optimised integration debuts Cadence team debuts a DDR4 IP solution and integration environment that claims to speed integration, reduce cost and ensure design manufacturability. |
| 2011-04-01 | ADCs dissipate <1mW/Msps from 1.8V Linear's LTC2145 family of ultra-low-power 14bit and 12bit ADCs offering 25Msps to 125Msps performance with less than 1mW/Msps power dissipation from a 1.8V supply. |
| 2011-01-31 | GUI-based compiler simplifies DDR PHY assembly GUI-based compiler simplifies DDR PHY assembly |
| 2010-12-23 | 65nm SRAMs reduce power consumption up to 50% Cypress unveils its high-density QDRII+ SRAM portfolio with 65nm 36Mbit and 18Mbit devices offering reduced power consumption up to 50 per cent compared with 90nm SRAMs. |
| 2010-08-23 | Network processors pack DDR3, USB 3.0 Ubicom presents the IP8100 family of network processors with multiple integrated interfaces such as DDR3, USB 3.0 are geared towards next generation solutions for consumers, SOHO and SMB. |
| 2010-08-03 | Motherboard for 45nm processor uses dual channel mem Gigabyte Technology reveals the GA-G41M-Combo motherboard for the 45nm Intel multi-core processor that supports both DDR2 and DDR3 RAM. |
| 2010-07-28 | Samsung,Toshiba team on DDR 2.0 NAND Samsung,Toshiba team on DDR 2.0 NAND |
| 2010-06-21 | 512GB SSD uses toggle-mode DDR NAND 512GB SSD uses toggle-mode DDR NAND |
| 2010-06-07 | Overcome debugging challenges in DDR memory Overcome debugging challenges in DDR memory |
| 2010-05-28 | Cadence, IBM team on high performance IPs Cadence Design Systems, Inc. and IBM have signed an agreement to develop DDR PHYs, memory controllers, and protocols such as PCIe and Ethernet under 32-nanometer silicon-on-insulator. |
| 2010-05-10 | Buck regulator enables user-programmable frequency Linear Technology debuts the LTC3615, a synchronous buck regulator that operates from an input voltage of 2.25V to 5.5V, making it suitable for single-cell Li-ion applications as well as 3.3V and 5V intermediate bus systems. |
| 2010-05-10 | Configuring the SPEAr600 multi-port memory controller (MPMC) for external DDR SDRAM Configuring the SPEAr600 multi-port memory controller (MPMC) for external DDR SDRAM |
| 2010-04-28 | Fully programmable DSP family enables flexible design From Freescale comes the multi-core MSC825x DSP family with features such as multiple DDR controllers, two Serial RapidIO interfaces and a PCI Express interface to make designing highly flexible. |
| 2010-04-27 | Interfacing DDR memories with the i.MX31 Interfacing DDR memories with the i.MX31 |
| 2010-04-13 | Power controller simplifies EMI filtering designs Exar Corp. has expanded its range of low-voltage, step-down controllers specifically targeted at DDR memory power architectures. |
| 2010-04-13 | Single PHY chip supports multiple DDR standards Single PHY chip supports multiple DDR standards |
| 2010-02-23 | i.MX51 DDR/mDDR calibration procedure i.MX51 DDR/mDDR calibration procedure |
| 2010-02-17 | PowerQUICC and QorIQ DDR3 SDRAM controller register setting considerations This application note expands on the description of the DDR3 memory controller programmable registers in the PowerQUICC and QorIQ processor reference manuals. |
| 2010-02-15 | Hardware and layout design considerations for DDR3 SDRAM memory interfaces This application note aims to minimise board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. |
| 2009-10-20 | 114Mbit SRAMs target networking applications Cypress' 65nm QDR and DDR SRAMs offer up to 50 per cent lower standby and dynamic current consumption. |
| 2009-10-16 | DDR SDRAM shortage to last until Q1 10 DDR SDRAM shortage to last until Q1 10 |
| 2009-09-21 | Embedded ACPI compliant DDR power generation using the ISL6537 and ISL6506 Embedded ACPI compliant DDR power generation using the ISL6537 and ISL6506 |
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