What is DDR2?
| Acronym for Double-Data-Rate Two, which refers to a computer memory technology as it applies to synchronous dynamic random access memory (SDRAM). Standards are defined for the ICs as well as the DIMMs they enable. A single-data-rate SDRAM transfers data on every rising edge of the clock pulse 100MHz. Both DDR and DDR2 are double pumped—they transfer data on the rising and falling edges of the clock, achieving an effective rate of 200MHz with the same clock frequency. The difference between DDR2 to DDR is a doubled bus frequency for the same physical clock rate, which doubles the data rate yet another time. |
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| 2012-05-21 | Samsung starts mass production of 20nm DRAM chips Korean giant Samsung has begun producing 4 GB low power DDR2 (LPDDR2) memory using its 20nm-class process node. |
| 2012-01-23 | Samsung eMCPs target mid-level smartphones Samsung's embedded memory solutions tip 30nm low power DDR2 DRAM and 20nm NAND flash memory to meet the need for advanced software and increased data storage in smartphones and tablets. |
| 2011-07-27 | ARM-based evaluation kit offers USB Wi-Fi module Embest debuts the DevKit7000 evaluation board that includes 1GHz Samsung S5PV210 ARM Cortex-A8 application processor, onboard 512Mb DDR2 RAM and 512Mb NAND flash with preloaded Android 2.3. |
| 2011-07-12 | ±6A switching regulator targets DDR termination Linear's LTC3617 is a step-down switching regulator that generates bus termination voltage for DDR/DDR2/DDR3 and future standard memory applications that require current sourcing and sinking. |
| 2011-04-14 | SH7785 initial settings sample program Here's a sample program for setting the initialisation items required at SH7785 start-up. |
| 2011-03-18 | ONFI 3.0 NAND specification released The new ONFI 3.0 standard for simplifying the integration of NAND flash memory into CE devices, uses the non-volatile DDR2 (NV-DDR2) interface enabling speeds of up to 400MBit/s. |
| 2011-03-16 | Apple A5 analysis reveals Samsung make UBM TechInsights' teardown analysis of the A5 chip inside Apple iPad 2 reveals that Samsung has made the A5 chip contrary to recent reports about Apple's foundry alliance with TSMC for the A5. |
| 2010-12-10 | Implement DDR2 SDRAM interface in FPGA Implement DDR2 SDRAM interface in FPGA |
| 2010-11-08 | DDR2 SDRAM offers 256Mb density support DDR2 SDRAM offers 256Mb density support |
| 2010-08-03 | Motherboard for 45nm processor uses dual channel mem Gigabyte Technology reveals the GA-G41M-Combo motherboard for the 45nm Intel multi-core processor that supports both DDR2 and DDR3 RAM. |
| 2010-07-23 | DDR2 SO-DIMMs suit laptops, tablet PC DDR2 SO-DIMMs suit laptops, tablet PC |
| 2010-05-10 | Configuring the SPEAr600 multi-port memory controller (MPMC) for external DDR SDRAM This application note describes how to configure the MPMC to use different types of DDR and DDR2 memories, and tune the parameters in accordance with JEDEC requirements and the flexibility available in the application. |
| 2010-05-04 | Interfacing mDDR and DDR2 memories with the i.MX51 Interfacing mDDR and DDR2 memories with the i.MX51 |
| 2010-04-27 | Monolithic 2Gbit LPDDR2 operates at 1.2V Micron Technology Inc. unveils monolithic 2Gbit LPDDR2 memory chips that can be used as a stand-alone device or in combination with NAND for high-capacity multi-chip package or package-on-package solutions. |
| 2010-03-26 | Interfacing mDDR and DDR2 memories with i.MX25 Interfacing mDDR and DDR2 memories with i.MX25 |
| 2010-03-15 | USB 2.0 FPGA module enables instant reprogramming Opal Kelly debuts the USB 2.0 integrated FPGA module based on Xilinx Virtex-5 FPGA that delivers 256MB DDR2, 36Mbit SRAM, 32Mbit flash and up to 200 high-speed user I/Os. |
| 2010-02-23 | i.MX51 DDR/mDDR calibration procedure This application note describes the calibration procedure to find the optimal delay line settings for the i.MX51, to work with Mobile DDR (double data rate) or DDR2 (extended version of DDR) memories. |
| 2010-02-03 | High-speed DDR2 SDRAM suits automotive, net apps High-speed DDR2 SDRAM suits automotive, net apps |
| 2010-01-25 | Implementing DDR2/mDDR PCB layout on the TMS320DM335 DMSoC Implementing DDR2/mDDR PCB layout on the TMS320DM335 DMSoC |
| 2009-12-01 | Atom-based COM Express supports up to 2GB DDR2 Atom-based COM Express supports up to 2GB DDR2 |
| 2009-08-03 | ARM MPUs with DDR2 target industrial apps ARM MPUs with DDR2 target industrial apps |
| 2009-08-03 | DDR3 SDRAM shortage to continue in Q3 Market analysts are forecasting DDR3 and DDR2 SDRAM shortages. |
| 2009-07-08 | Guide to LatticeSC/M DDR/DDR2 SDRAM memory interface Guide to LatticeSC/M DDR/DDR2 SDRAM memory interface |
| 2009-06-05 | Memory model generator cuts verification time eInfochips has announced the availability of a DDR2 SDRAM SystemVerilog Memory Model Generator. |
| 2009-05-28 | Guide to using LatticeECP3 I/O interface Know how to use the capabilities of the LatticeECP3 devices to implement high-speed generic DDR interface, and the DDR, DDR2 and DDR3 memory interfaces. |
| 2009-04-29 | First 54nm 1GB DDR2 DRAM consumes low power First 54nm 1GB DDR2 DRAM consumes low power |
| 2009-04-02 | DRAM supply bit growth only 2.43% in '09 DRAMeXchange forecasts a 2.43 per cent bit growth, compared to 95 per cent in 2007 and 66 per cent in 2008. |
| 2009-02-17 | LPDDR2 portfolio targets mobile, consumer apps Micron Technology Inc. has expanded its efforts in the NAND and mobile DRAM arenas. |
| 2009-02-10 | Migrate from MPC834x revision 1.x to 3.x Know the differences between MPC834x revisions 1.x and 3.x with respect to software, hardware, internal module revision and chip pin assignment. |
| 2009-02-06 | First validated 40nm DRAM chip announced Samsung has announced the first 40nm DRAM chip and module, a 1Gbit DDR2 compliant device. |
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