What is design for manufacturability (DFM)?
| The design methodology called "design for manufacturability" (DFM) includes a set of techniques used to modify the design of semiconductors in order to make them more manufacturable by improving their functional yield, parametric yield, reliability etc. |
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| 2012-03-05 | Samsung's 20 nm DFM based on Mentor's Calibre platform Samsung's 20 nm DFM based on Mentor's Calibre platform |
| 2012-02-07 | Cadence, Samsung collaborate on DFM solution Cadence, Samsung collaborate on DFM solution |
| 2012-01-25 | Fujitsu opts for Mentor's Calibre platform Mentor Graphics reports that Fujitsu has adopted the latest Calibre physical verification and design for manufacturing (DFM) capabilities in its analogue and digital design flows. |
| 2012-01-20 | How to employ critical area analysis Critical area analysis is a DFM technique that measures the susceptibility of a specific layout to random defects and indicates areas of the layout where design modifications can have the greatest positive impact on overall yield. |
| 2011-09-21 | Fujitsu adopts Cadence DFM tools for 28nm design Fujitsu adopts Cadence DFM tools for 28nm design |
| 2011-02-21 | Evolution of manufacturing closure for advanced nodes (Part 3) Learn how performing signoff DRC/DFM verification within the place and route environment affects the design flow and improves time to closure. |
| 2011-02-10 | VIA adopts Mentor's Calibre PERC for ESD protection VIA Technologies Inc. adopts Mentor Graphics Corp.'s Calibre PERC electrical rule checking product for enabling ESD protection on its x86 processor platforms. |
| 2011-02-14 | Evolution of manufacturing closure for advanced nodes (Part 2) Part 2 of this article series tackles how to bring signoff into place and route. |
| 2011-02-01 | Ease production at 65nm with DFM Ease production at 65nm with DFM |
| 2011-01-20 | Test chip primed for 32/28nm HKMG IC manufacture Mentor Graphics reports its collaboration with Common Platform Alliance members to design a test chip using its netlist-to-GDSII solution for CPA 32/28nm high-k metal gate IC manufacturing. |
| 2010-01-15 | Mentor, Freescale partner on test, verification Freescale Semiconductor has selected Mentor Graphics Corp. as a partner in the silicon test, yield analysis, and physical verification technology areas. |
| 2010-01-13 | Designing for the next upturn Mentor Graphics chairman and CEO, Walden Rhines, says that while India’s share in the semiconductor market will grow at 6.4 times the global CAGR, the road ahead is not without its challenges. |
| 2009-10-26 | Putting the DFM puzzle together Putting the DFM puzzle together |
| 2009-08-05 | DAC panel revives DFM debate DAC panel revives DFM debate |
| 2009-04-23 | IMEC sends DFM tool for embedded SRAMs to Samsung IMEC sends DFM tool for embedded SRAMs to Samsung |
| 2009-03-24 | Mentor: Process variability is not all bad According to Mentor execs, process variability could be considered a competitive advantage if properly dealt with. |
| 2009-02-27 | Team-up to develop co-optimised design solutions TSMC and Tela will also enhance the PowerTrim Service based on Blaze DFM's patented gate CD biasing technology. |
| 2009-02-23 | Made in India: DFM tool checks, analyses in single session Made in India: DFM tool checks, analyses in single session |
| 2008-12-22 | Overcome 45nm P&R challenges Read about the tools that offer MCMM timing analysis and other features to handle the challenges of 45nm IC design. |
| 2007-05-25 | In the eye of the DFM/DFY storm In the eye of the DFM/DFY storm |
| 2008-09-25 | Test data provides yield improvement metrics Speculation of the value of DFM or DFY technology can be easily delineated by validating simulated or predicted results using test data from wafer probe. |
| 2008-08-01 | TSMC rolls out new DFM scheme TSMC rolls out new DFM scheme |
| 2007-12-04 | Using DFM routing to impact design performance and yield Using DFM routing to impact design performance and yield |
| 2008-06-12 | TSMC aims to unify 32nm design flow TSMC faces the 32nm challenge with a new design-for-manufacturing scheme. |
| 2008-06-03 | Planarity flow qualified for TSMC's IC manufacturing Mentor Graphics' calibre model-based planarity flow has qualified for TSMC's 65 and 40nm processes. |
| 2008-05-27 | Analysis: The DFM mix Analysis: The DFM mix |
| 2008-01-16 | DFM-oriented test ensures better yield DFM-oriented test ensures better yield |
| 2008-01-01 | EDA tools allow integrated die, package design The EDA industry is adapting to provide designers with tools that allow them to work on the entire system, not just parts that have different physical characteristics. |
| 2007-09-24 | Magma, UMC team release verification, DFM tools for 65nm Magma, UMC team release verification, DFM tools for 65nm |
| 2007-09-21 | Chip makers, EDA vendors set up DFM coalition Chip makers, EDA vendors set up DFM coalition |
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