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| 2011-03-15 | Mentor touts instantaneous signoff verification Mentor Graphics Corp. unveils its Calibre physical verification platform offering instantaneous design rule checking (DRC) to allow signoff-quality verification in the design creation phase. |
| 2011-02-21 | Evolution of manufacturing closure for advanced nodes (Part 3) Learn how performing signoff DRC/DFM verification within the place and route environment affects the design flow and improves time to closure. |
| 2011-02-14 | Evolution of manufacturing closure for advanced nodes (Part 2) Part 2 of this article series tackles how to bring signoff into place and route. |
| 2010-08-30 | Magma Design Automation is the latest member of DFMC Magma Design Automation is the latest member of Si2's Design For Manufacturability Coalition (DFMC). |
| 2010-08-27 | Physical verification solutions aid 65nm transition Magma Design Automation Inc. unveils scalable physical verification solutions that offer fast turnaround time for designs at the 65nm node and below. |
| 2010-08-12 | Magma tools verify TSMC's 28nm PQV chip test Magma's physical verification software—Quartz DRC has delivered sign-off accuracy for TSMC's 28nm product qualification vehicle (PQV) test chip. |
| 2010-07-28 | TAS57xx dynamic range control This application report provides background information, general equations and instructions for proper use of the Texas Instruments TAS57xx series dynamic range control (DRC). |
| 2010-05-25 | The benefits of creating patterns As design nodes drop below 45nm, design rules are exploding in number and complexity, making design rule checking (DRC) harder and lengthier. |
| 2009-05-18 | Incremental DRC for chip verification Incremental DRC for chip verification |
| 2009-05-08 | Physical verification tools offer free trial Magma Design Automation has introduced the Quartz DRC and Quartz LVS 2009.05 physical verification tools. |
| 2009-02-12 | Verification tools tout faster runtime The latest Quartz DRC and Quartz LVS from Magma offer significant runtime improvement. |
| 2009-01-15 | Audio IC includes MultiBand DRC feature Audio IC includes MultiBand DRC feature |
| 2008-10-10 | Mentor, TSMC partner on physical verification solutions TSMC and Mentor collaborated on PV solutions leveraging a new feature of the "Equation-Based DRC." |
| 2007-05-30 | Routing suite addresses 45nm challenges Sierra Design Automation's enhanced Olympus-SoC placement and routing suite addresses 45nm IC physical design challenges such as interconnect resistance. |
| 2006-09-08 | HyperTransport Consortium gets seven new members Seven companies recently joined the HyperTransport Technology Consortium as part of its commercial membership base. |
| 2006-07-19 | DRC tool solves yield challenges of nanometre era DRC tool solves yield challenges of nanometre era |
| 2000-12-01 | Integrated approach for emerging tech designs This technology article describes the integration of clock tree synthesis with logic synthesis, placement route and interconnect extraction to maximize the potentials of cell-based designs. |
| 2001-05-16 | Practical IC design in the sub-wavelength regime Demonstrated success of sub-wavelength lithographic processes has created the demand for a more robust, comprehensive design flow. |
| 2001-05-28 | Removing ERC and DRC error indicators Removing ERC and DRC error indicators |
| 2001-06-22 | Solution space analysis for high-speed design Up-front SI analysis can drive placement and routing while providing a viable alternative to the old "route-analyze-fix" approach of yesteryear. |
| 2001-07-16 | Validate EMC design rules with 3D simulation This article provides an overview of EMC- and 3D-analysis tool capabilities that can enhance an your design's performance. |
| 2002-02-16 | Mastering full-custom layout design This technical article assists readers in defining the various flavors of full-custom layout design for them to choose the right type of tool for the right type of job. |
| 2003-05-02 | Eliminating the problems of dual physical verification A single verification tool that can perform fast interactive verification on cells and blocks, as well as fast and accurate batch verification on full-chip SoCs, is essential to meet today's time-to-market schedules. |
| 2004-02-02 | Write your own PCB design rule checker After PCB design is captured in a schematic tool, a design rule checker (DRC) must be run to find any design rule violations. This must be done before backend processing starts. |
| 2004-08-16 | Timing closure: Hybrid optimization to the rescue Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure. |
| 2005-05-16 | Across the flow: DFM's many faces EDA toolmakers, designers forge partnership to develop new DFM process flow |
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