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| 2012-04-18 | Synopsys IP sub-system optimises audio SoCs Synopsys' DesignWare SoundWave Audio Sub-system is touted as a complete, integrated hardware and software audio IP sub-system for SoC designs. |
| 2012-02-21 | HDMI 1.4 PHY IP available in 28nm Synopsys releases DesignWare HDMI 1.4 PHY IP optimised for low power, small area and high performance at 28nm. |
| 2012-02-16 | Synopsys IP optimises 28nm SoC performance Synopsys' DesignWare Embedded Memory and Logic Library IP are aimed at optimising 28m SoCs for enhanced performance and low power consumption. |
| 2011-05-12 | SuperSpeed USB 3.0 PHY IP achieves certification Synopsys Inc. achieves USB Implementers Forum (USB-IF) SuperSpeed USB certification for its DesignWare SuperSpeed USB 3.0 xHCI (Extensible Host Controller Interface) IP. |
| 2011-03-04 | DesignWare IP supports PCIe 3.0 specs DesignWare IP supports PCIe 3.0 specs |
| 2011-01-31 | GUI-based compiler simplifies DDR PHY assembly Synopsys Inc. releases a GUI-based DesignWare DDR PHY compiler for SoCs offering ease in assembly of a customised, high-performance DDR PHY. |
| 2011-01-17 | Configurable processor core gets Android OS support Synopsys reveals that Android OS (v2.2 FroYo) support is now available for its DesignWare ARC 750D processor addressing the needs of low-power, cost-sensitive portable and consumer applications. |
| 2010-11-23 | Dual-core processor optimised for HD audio apps Synopsys Inc. offers the DesignWare ARC AS 221 BD dual-core processor for BluRay players and enhancements for the DesignWare ARC 600 family that cuts SoC power and silicon area |
| 2010-11-09 | SoC design IP reduces soft error rates Synopsys rolls out the DesignWare Self-Test and Repair Error Correcting Codes IP offering automated design implementation and test diagnostic flow to reduce the embedded memory transient errors. |
| 2010-11-02 | HDMI certified 1.4a Tx solution available for 40nm Synopsys reveals that its DesignWare HDMI 1.4a transmitter (Tx) digital controller and PHY IP solutions in the 40nm process node have achieved HDMI certification. |
| 2010-09-01 | 40nm M-PHY IP tailored for mobile devices Synopsys Inc. has released the DesignWare MIPI M-PHY IP offering next-generation high-speed interfaces based on the newly ratified MIPI Alliance M-PHY specification. |
| 2010-08-13 | Synopsys brings together USB software providers Synopsys Inc., forms the DesignWare USB Software Alliance Programme to help designers quickly incorporate USB connectivity into their SoCs with less risk and provide consumers with the plug-and-play functionality required for PCs, peripherals, mobile devices and consumer electronic products. |
| 2010-08-09 | Synopsys, GlobalFoundries extend relation to 28nm Synopsys Inc. and GlobalFoundries Inc. are extending their long standing relationship to the development of DesignWare interface PHY IP for use on a 28nm process. |
| 2010-08-02 | Modular Hi-Fi audio IP offered in 40nm, 55nm processes Synopsys Inc. debuts its low power, compact, modular DesignWare 96dB Hi-Fi audio IP in the 40nm and 55nm process technologies to add to its broad portfolio of high-quality audio IP solutions. |
| 2010-07-12 | Open-Silicon boasts 100% IP-silicon integration Synopsys Inc. has revealed that Open-Silicon has licensed and integrated 50 high-speed DesignWare IP products into customers' chips with 100 per cent first-pass silicon success. |
| 2010-06-16 | Synopsys to pay Rs.1,454.58 crore for Virage Logic Virage Logic will complement Synopsys' DesignWare interface and analogue IP portfolio by adding embedded memories with test and repair, non-volatile memories, standard cell libraries, and programmable cores for control and multimedia sub-systems. |
| 2010-06-02 | Ethernet controller IP targets A/V streaming Synopsys' DesignWare Ethernet Quality-of-Service (QoS) controller IP implements the new IEEE specifications for audio/video bridging features. |
| 2010-05-13 | Controller IP meets MIPI DigRF v4 1.00 specs From Synopsys Inc., comes the DesignWare MIPI (Mobile Industry Processor Interface) 4G DigRF Master Controller IP that’s suits LTE and WiMAX applications. |
| 2010-04-13 | Single PHY chip supports multiple DDR standards Synopsys, Inc. has rolled out the DesignWare DDR multiPHY which supports six DDR SDRAM standards in a single PHY without compromising on power consumption or silicon area. |
| 2009-04-27 | Jungo-Synopsys solution supports SuperSpeed USB Jungo's USBware for SuperSpeed USB 3.0 stacks will be integrated with the Synopsys DesignWare SuperSpeed USB IP offering. |
| 2009-03-31 | Design power-aware FPGAs, Part 3 Here are some techniques to eliminate or reduce the propagation of unnecessary glitches. |
| 2009-02-17 | Synopsys launches verification IP alliance program Initial members in the DesignWare VIP Alliance program include eInfochips and NoBug. |
| 2009-01-23 | Ethernet IP now supports IEEE 1588 spec Synopsys, Inc. says it has enhanced the DesignWare Ethernet MAC 10/100/1G IP. |
| 2008-08-19 | DDR IP portfolio targets SoC designs Synopsys has announced the availability of silicon- proven DesignWare DDR IP solutions for SoCs. |
| 2008-07-25 | Low-power embedded microprocessor cores debut Synopsys announced the availability of fully synthesisable implementations of the IBM PowerPC 460. |
| 2008-07-22 | Synopsys expands DesignWare SATA solution Synopsys expands DesignWare SATA solution |
| 2008-05-29 | Design library target FPGA synthesis EVE introduced its DesignWare foundation library for use with FPGA synthesis software. |
| 2008-02-12 | USB IP reduces power, area Synopsys has developed DesignWare USB LPM and HSIC digital controller and PHY IP that reduces power consumption and area for USB-enabled chips. |
| 2007-09-20 | Synopsys unveils system-level library Synopsys' DesignWare System-Level Library provides SystemC transaction-level simulation models for assembling virtual platforms. |
| 2007-07-05 | Synopsys, UMC collaborate on 65/90nm connectivity IP Synopsys has collaborated with UMC to port its DesignWare USB 2.0, PCI Express, SATA and XAUI PHY semiconductor IP to UMC's 90nm and 65nm technologies. |
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