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| 2011-02-21 | Evolution of manufacturing closure for advanced nodes (Part 3) Learn how performing signoff DRC/DFM verification within the place and route environment affects the design flow and improves time to closure. |
| 2011-01-21 | TDKs support BCDMOS chip design at 0.35/0.18µm TDKs support BCDMOS chip design at 0.35/0.18µm |
| 2010-11-24 | TSMC qualifies Synopsys' IC Validator TSMC qualifies Synopsys' IC Validator |
| 2010-06-23 | DAC panel debates 3D TSV future A panel at the Design Automation Conference (DAC) debated on the roadmap for 3D through-silicon-via (TSV) interconnects. |
| 2010-03-08 | iPDK open standard released IC foundries and IDMs can use this standard to build a single iPDK that works with multiple OpenAccess-based custom design tools to cut development costs and support for vendor-specific PDKs. |
| 2009-04-29 | Talus IC implementation system supports CPF Talus IC implementation system supports CPF |
| 2009-02-12 | Verification tools tout faster runtime The latest Quartz DRC and Quartz LVS from Magma offer significant runtime improvement. |
| 2008-12-23 | Synopsys, ST team up on 32nm design flow Synopsys, ST team up on 32nm design flow |
| 2008-06-05 | TSMC introduces 40-nm design flow TSMC introduces 40-nm design flow |
| 2007-01-29 | Architect, design, implement, and verify low-power digital ICs Architect, design, implement, and verify low-power digital ICs |
| 2007-07-24 | Sequence tool enhances Faraday low power design flow Sequence tool enhances Faraday low power design flow |
| 2007-07-16 | TSMC bridges design-manufacturing gap TSMC bridges design-manufacturing gap |
| 2007-07-06 | p-cell tech donation leads to interoperable design flow p-cell tech donation leads to interoperable design flow |
| 2007-06-18 | Advanced low-power modes stump IC designers Advanced low-power modes stump IC designers |
| 2007-05-08 | IC analysis tool refines chip architecture IC analysis tool refines chip architecture |
| 2007-04-25 | Common Platform partners roll 65nm reference flow Common Platform partners roll 65nm reference flow |
| 2007-04-02 | Synopsys rolls design platform supporting UPF 1.0 Synopsys rolls design platform supporting UPF 1.0 |
| 2007-03-05 | Freescale reports reduction in EDA tool flow Freescale reports reduction in EDA tool flow |
| 2006-09-18 | EDA rivals spar over power issues Any EDA vendor or large EDA user will tell you there's a compelling need for a standard way to express power-management intent throughout the IC design flow. The problem is that two separate groups are working towards that objective, amid profound disagreements over how to get there. |
| 2006-09-12 | Magma, SMIC announce 90nm ref flow Magma, SMIC announce 90nm ref flow |
| 2006-07-21 | TSMC ref flow integrates Cadence digital design IC platform TSMC ref flow integrates Cadence digital design IC platform |
| 2006-07-18 | Magma preps DAC demonstrations Magma will demonstrate the capabilities of its Talus IC implementation system, methods for minimizing power consumption, and DFM capabilities integrated in the design flow at next week's DAC. |
| 2006-04-24 | Software provides 3D temperature analysis Gradient Design Automation launched CircuitFire, a software product that provides 3D temperature analysis integrated directly into the IC design flow. |
| 2005-12-01 | Manufacturing moves into IC design flow Manufacturing moves into IC design flow |
| 2005-08-31 | Tensilica enhances methodology for 90nm design flow Tensilica enhances methodology for 90nm design flow |
| 2005-09-16 | When infrastructure is essence: Open-Silicon automates the flow When infrastructure is essence: Open-Silicon automates the flow |
| 2001-05-16 | Practical IC design in the sub-wavelength regime Practical IC design in the sub-wavelength regime |
| 2001-08-09 | Contactless smartcard design using the EM simulation software Contactless smartcard design using the EM simulation software |
| 2001-09-16 | Hopper hierarchical flow: Improvements for large ICs Hopper hierarchical flow: Improvements for large ICs |
| 2001-12-01 | The work flow of a block-based design team The work flow of a block-based design team |
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