What does IC design verification mean?
| IC design verification refers to the process of determining whether or not the design of a product, of a given development phase, satisfies the conditions imposed from the start. |
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| 2011-12-14 | Globalfoundries certifies Synopsys IC validator Globalfoundries certifies Synopsys IC validator |
| 2011-07-29 | IC design platform automates routing tech IC design platform automates routing tech |
| 2011-02-21 | Evolution of manufacturing closure for advanced nodes (Part 3) Learn how performing signoff DRC/DFM verification within the place and route environment affects the design flow and improves time to closure. |
| 2009-06-05 | Synopsys CEO: Crisis presents opportunities The IC industry is headed for increasing challenges from higher design costs and production at smaller geometries. |
| 2009-05-28 | Exar to use Synopsys platforms for 65nm designs Exar has signed an expanded business agreement to establish Synopsys as its leading EDA partner. |
| 2009-05-20 | Team-up enables MEMS/IC co-design, co-verification Team-up enables MEMS/IC co-design, co-verification |
| 2009-05-13 | Synopsys launches IC Validator Synopsys launches IC Validator |
| 2009-04-30 | IC verification: Coverage vs. qualification IC verification: Coverage vs. qualification |
| 2009-03-02 | Jasper launches new verification tools Jasper launches new verification tools |
| 2009-02-12 | Verification tools tout faster runtime Verification tools tout faster runtime |
| 2008-10-14 | EDA revenue weakens in Q2 EDA industry revenue declined to Rs.5,838.26 crore ($1357.4 million), compared to Rs.6,059.33 crore ($1408.8 million) in Q2 2007. |
| 2007-01-29 | Architect, design, implement, and verify low-power digital ICs To enable the adoption of advanced low-power techniques by mainstream users, there is a need for a design flow that holistically addresses the architecture, design, verification, and implementation of low-power designs. |
| 2007-05-02 | Commoditisation threatens ASIC business The tumultuous ASIC business is undergoing a shakeout amid soaring design, verification and mask costs, coupled with the economic realities in the market. |
| 2007-04-02 | Synopsys rolls design platform supporting UPF 1.0 Synopsys Inc. has announced a low-power design flow that will implement the Accellera Unified Power Format version 1.0 in its IC verification and implementation products in the second half of 2007. |
| 2007-03-28 | Use timing-accurate system-level models A virtual system prototype provides a software simulation-based model of the electronic system that allows design teams to improve design productivity, reduce time-to-market and decrease risk. |
| 2007-03-23 | Planning the verification process with SystemVerilog Planning the verification process with SystemVerilog |
| 2007-03-19 | China climbs further up the design ladder The design industry of China continues to be enveloped with fervor as local companies and the big names in the electronics field come together to deliver new products, technologies and solutions to a captive audience worldwide. |
| 2007-03-15 | Cadence solution enables Taiwan's first 65nm IC design Cadence solution enables Taiwan's first 65nm IC design |
| 2007-03-05 | Freescale reports reduction in EDA tool flow Freescale Semiconductor has reported significant design efficiency improvements and a sizeable reduction in the number of EDA "tool flows". |
| 2007-02-27 | EDA 'troublemakers' debate at DVCon EDA vendor The annual "EDA Bigwigs" panel at the Design and Verification Conference (DVCon) was renamed the "Troublemaker's Panel" this year for good reason. Confronted with provocative questions, DVCon EDA vendor representatives debated topics such as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India. |
| 2007-02-14 | Statistical tool avoids overdesign Solido Design Automation has taken the wraps off technology that will provide transistor-level statistical design and verification. The company promises to take Monte Carlo analysis "to the next level" with additional capabilities. |
| 2007-01-15 | Mentor, EVE settle patent infringement case Mentor Graphics Corp. and emulation provider EVE Corp. have settled a previously unpublicised patent infringement lawsuit, disclosed the two companies. The legal action was pending in the United States District Court of Oregon. |
| 2006-12-22 | India's IC industry needs 'pull strategy', says ISA India's IC industry needs 'pull strategy', says ISA |
| 2006-12-21 | Chip designers satisfied with IC verification environments Chip designers satisfied with IC verification environments |
| 2006-10-16 | Engineers publish book on IC verification Engineers publish book on IC verification |
| 2006-09-06 | Engineers launch free open source website for C++ verification Engineers launch free open source website for C++ verification |
| 2006-08-23 | GiQuila adopts Mentor's hardware verification system for handheld devices GiQuila adopts Mentor's hardware verification system for handheld devices |
| 2006-07-19 | AWR, Helic partner in VeloceRF technology AWR and Helic S.A. have announced a technology licensing agreement that enables the integration of Helic's VeloceRF whole-chip RF extraction, modelling and verification technology into AWR's Analog Office RF IC design suite. |
| 2006-06-01 | Breaking the IC verification barrier Breaking the IC verification barrier |
| 2006-04-18 | Synopsys offers RTL-to-GDSII design system Synopsys Inc. is offering its customers the Pilot Design Environment, an integrated RTL-to-GDSII design system tailored to each customer's design infrastructure. |
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