What are PLDs?
| PLDs or programmable logic devices refer to a variety of logic chips that are programmable at the user's site. Programmability of logic means that new chip designs can be tested and easily changed without incurring the huge photomask costs for chips completed in a fab. In addition, memory-based PLDs can be reprogrammed over and over, which allows working products to be upgraded at the user's site. |
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| 2012-04-30 | Lattice low-power PL devices aim for space-constrained apps Lattice Semiconductor debuts the low cost, low power MachXO2 family of devices (PLD) in a new 32 QFN (Quad Flatpack No-leads) package for space-constrained applications. |
| 2011-11-02 | FPGA replaces large capacity ASICs Xilinx offers Virtex-7 2000T FPGA that is touted as the industry's highest-capacity programmable logic device (PLD) built using 680 crore transistors. |
| 2011-05-25 | MachXO2 PLD family gains programming support MachXO2 PLD family gains programming support |
| 2011-05-05 | Intel makes foundry deal with PLD start-up, Tabula Intel makes foundry deal with PLD start-up, Tabula |
| 2010-03-03 | PLD architecture trades off time with circuit density PLD architecture trades off time with circuit density |
| 2009-11-11 | PLDs surprisingly thrive in downturn The current IC industry downturn created a good opportunity for the programmable logic device (PLD) segment, according to Altera president and CEO John Daane. |
| 2009-11-11 | Using a discrete crystal as a PLD clock source Using a discrete crystal as a PLD clock source |
| 2009-04-13 | FIFO Dipstick with Warp2 VHDL, CY7C371 Here's a method by which FIFOs of any size may be monitored by an external PLD which will then generate all of the flags necessary for most FIFO applications. |
| 2008-11-13 | Crime-fighters get PL edge PLD solutions offer high performance, flexibility and cost-effectiveness making it ideal for crime-fighting applications. |
| 2008-11-12 | J Drive: ISC for IEEE Standard 1532 devices The J Drive programming engine offers direct in-system configuration support for IEEE Standard 1532 PLD. |
| 2008-10-30 | FPGAs target portable consumer market Actel claims to have regained the price point record in the PLD arena with the "nano" versions of its FPGAs. |
| 2008-08-26 | Actel outlines PLD strategy Actel outlines PLD strategy |
| 2008-08-06 | Broadcast video infrastructure implementation using FPGAs With expanding resolutions and evolving compression, there is a need for high performance while keeping architectures flexible to allow for quick upgradeability. By providing solutions for these needs, PLDs play an important role for the emerging digital video broadcast infrastructure. |
| 2005-09-26 | Low-power PLDs: a good choice for portable designs This article describes how to harness the key features of low-power PLDs for use in portable applications. |
| 2008-05-01 | Cut down processor power consumption with CPLD This article describes this possibility, along with types of operations that allow a processor to remain in a low-power state longer, thereby reducing system power consumption. |
| 2005-09-26 | Low-power PLDs: a good choice for portable designs This article describes how to harness the key features of low-power PLDs for use in portable applications. |
| 2007-05-29 | Standardized programmable power management for circuit boards This article discusses how to deal with the complexity of power management for modern circuit board design with the use of a standardized, programmable power management device. |
| 2007-11-16 | PLDs ease time-to-market pressures Today's devices provide the advantages of both an FPGA and a CPLD with a non-volatile, low-cost, instant-on high performance logic solution for applications that have traditionally used CPLDs. |
| 2007-04-27 | J drive: In-system programming of IEEE standard 1532 devices The configuration of in-system IEEE Standard 1532 PLDs require J Drive programming engine. The programming engine uses the configuration algorithm information from a 1532 Boundary Scan Description Language file and applies the data through the IEEE Standard 1149.1 test access port. |
| 2006-08-30 | Actel FPGAs cut power drain to target mobile market Actel has introduced a family of devices that it claims is the industry's lowest-power FPGAs in the market. |
| 2006-05-30 | FPGA, other PLD market to grow by 14% in '06 FPGA, other PLD market to grow by 14% in '06 |
| 2006-05-11 | PLD tool gets upgrade, supports 90nm FPGAs PLD tool gets upgrade, supports 90nm FPGAs |
| 2005-10-03 | 2005 Design Trends and EDA Tools: China & Taiwan IC and PCB design engineers in China and Taiwan reveal the current level of design and share development experience with EDA tools. |
| 2001-04-04 | Latches and flip-flops with PLS153 This application note discusses the use of the logic functions of the PLS153 PLD in implementing memory functions, such as latches and edge-triggered flip-flops, with a relatively small part of the chip and without external wiring. |
| 2001-03-19 | FLASH370i 5V to 12V dc-dc converter solutions This application note provides various solutions for the 12V super-voltage requirement for Cypress Semiconductor's Flash-based In-System Reprogrammable CPLDs in designs that do not already include a source for 12V. |
| 2003-12-20 | PCI bus target controller implementation using a Lattice CPLD This application note describes how to implement a PCI bus target controller using the company's CPLD products. |
| 2002-12-11 | Boundary Scan Testability with Lattice's sysIO Capability This application note describes how to perform Boundary Scan Test on devices with sysIO capability. |
| 2001-03-21 | Understanding bus-hold: A feature of Cypress CPLDs This application note covers the bus-hold feature of Cypress Semiconductor's FLASH370i, Ultra37000 and Ultra37000V families of CPLDs. |
| 2001-03-19 | Converting designs from FLASH370i to Ultra37000 devices This application note addresses the issues associated with upgrading a design from a FLASH370 or a FLASH370i CPLD to an Ultra37000 CPLD. |
| 2002-12-06 | Metastability in MACH Devices This application describes metastability in MACH devices, which occurs in digital systems where inputs are not synchronized to their own internal clocks. |
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