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| 2012-01-10 | PLL synthesisers aid apps design PLL synthesisers aid apps design |
| 2010-06-22 | LatticeECP2/M sysCLOCK PLL/DLL design and usage guide LatticeECP2/M sysCLOCK PLL/DLL design and usage guide |
| 2010-06-18 | Clock cleaner IC eliminates unwanted noise The Si5317 pin-controlled jitter cleaning clock IC requires no external PLL components, simplifying PCB design and layout in space-constrained applications while minimising the threat of board-level noise impacting jitter performance. |
| 2010-04-20 | A/V clock generator eliminates PLL tweaking A/V clock generator eliminates PLL tweaking |
| 2010-03-30 | MachXO sysCLOCK design and usage guide MachXO sysCLOCK design and usage guide |
| 2009-12-09 | Simplifying system design using the CS4350 PLL DAC Simplifying system design using the CS4350 PLL DAC |
| 2009-02-02 | Design tools ease RF systems design Design tools ease RF systems design |
| 2008-10-29 | Tool verifies PLL noise with true SPICE accuracy Tool verifies PLL noise with true SPICE accuracy |
| 2008-03-27 | Analogue FastSPICE breaks verification barrier Berkeley Design Automation has announced that the company's Analogue FastSPICE circuit simulator has delivered an industry first full-circuit PLL synthesiser performance simulation with true SPICE accuracy. |
| 2008-01-17 | Simulation of Proprietary Low Power Wireless Systems Proposes a simulation tool that designers can use for developing proprietary short-range wireless systems, while keeping within local regulatory requirements and design parameters. |
| 2008-02-12 | Simplifying PLL Design Simplifying PLL Design |
| 2007-05-18 | S/PDIF transceivers suppress jitter above 100Hz Wolfson Microelectronics' S/PDIF transceivers offer jitter suppression in audio data transfer at frequencies above 100Hz. |
| 2007-04-27 | APN1012: VCO designs for wireless handset and CATV set-top applications Due to the demand of band coverage by RF applications, most of the free running oscillators have become varactor-controlled oscillators (VCOs). The use of VCO together with the first PLL circuit realises band coverage which requires two sources of RF power. The reference source frequency is generally a VCXO or TCXO, while the other frequency is controlled by the PLL phase detector. The applications include wireless handset and CATV STBs. |
| 2006-11-16 | Design RFICs faster, accurately Design RFICs faster, accurately |
| 2006-05-01 | Xpedion introduces transistor-level closed loop PLL solution Xpedion introduces transistor-level closed loop PLL solution |
| 2002-08-16 | Hidden complexities of PLLs are revealed Measuring PLLs in a quiet, low-noise environment can yield optimistic and misleading jitter results. |
| 2000-11-27 | Design guidelines for PC100 registered SDRAM modules Design guidelines for PC100 registered SDRAM modules |
| 2000-12-05 | An improved PLL design method without natural frequency and damping An improved PLL design method without natural frequency and damping |
| 2000-12-13 | The MC145170 in basic HF and VHF oscillators This application note demonstrates how the MC145170 PLL chip can be implemented in a PLL frequency synthesizer design, along with an LPF and a VCO/VCM. |
| 2000-12-13 | Configuring and applying the MC74HC4046A phase-locked loop This application note is intended to show how to configure and apply the MC74HC4046A (HC4046A) PLL chip in a circuit design example with a reference frequency of 100kHz, an output frequency of 1MHz the center frequency and has the ability to move from 200kHz to 2MHz in 100kHz steps. |
| 2001-03-21 | Crystal oscillator topics This application note describes the recommended reference inputs for Cypress Semiconductor's PLL-based frequency synthesizers, and concludes with an error budget analysis. |
| 2001-04-02 | Designing Local Oscillators For CDMA Mobile Handsets This paper discusses the issues that affect local oscillator design for CDMA. Particularly, the performance, standards requirements and design approaches are explored using a PLL synthesizer. |
| 2001-04-15 | Hierarchical physical design for million-gate ASICs Hierarchical physical design for million-gate ASICs |
| 2001-04-26 | An introduction to the PLL library An introduction to the PLL library |
| 2001-09-16 | Hopper hierarchical flow: Improvements for large ICs This technical article describes the Hopper software hierarchical flow implemented to maximize large, high-performance IC design. |
| 2001-09-27 | The RC charge pump: A versatile RF library circuit for phase locked loops (PLL) and beyond The RC charge pump: A versatile RF library circuit for phase locked loops (PLL) and beyond |
| 2001-10-01 | Attending to signal integrity in complex designs This technical design article focuses on the signal integrity tools required to enhance the facilitation of IC design and processing. |
| 2002-02-01 | Being reasonable with design constraints Being reasonable with design constraints |
| 2002-02-16 | Mastering full-custom layout design Mastering full-custom layout design |
| 2002-05-03 | Using Z-COMM subminiature VCOs for WLAN systems This application note gives an overview of a 2.2GHz synthesizer design and offers design tips to help optimize performance with minimal development time. |
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