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| 2006-04-19 | Building reliable FPGA memory interface controllers This how-to article discusses various memory interface controller design challenges and the use of MIG to build a complete memory interface solution for your own application on a Virtex-4 FPGA. |
| 2007-03-28 | Tool automatically adds clock-gating logic to RTL code Tool automatically adds clock-gating logic to RTL code |
| 2007-01-10 | C-to-RTL compiler to generate full-chip designs C-to-RTL compiler to generate full-chip designs |
| 2007-01-09 | Verilog simulator offers faster RTL simulation Verilog simulator offers faster RTL simulation |
| 2006-07-14 | Debug tool helps faster RTL closure Debug tool helps faster RTL closure |
| 2001-05-01 | Cadence's 'all-in-one' tool gets skeptic reviews Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises. |
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