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| 2012-04-18 | Achieving early and accurate power analysis RTL power analysis offers the right trade-offs between accuracy and the ability to design for lower power. |
| 2012-03-09 | Cadence digital flow accelerates 20nm design Cadence digital flow accelerates 20nm design |
| 2011-11-15 | RTL tech optimised for power-sensitive apps RTL tech optimised for power-sensitive apps |
| 2011-10-26 | Avoiding RTL coding mistakes Avoiding RTL coding mistakes |
| 2011-09-16 | DSP design flow aims for medical imaging DSP design flow aims for medical imaging |
| 2011-06-03 | Atrenta releases RTL design textbook Atrenta releases RTL design textbook |
| 2011-05-05 | NVIDIA licenses NextOp's BugScope Graphics company NVIDIA signs a multi-licence agreement with NextOp Software Inc. for expanded use of NextOp's BugScope assertion synthesis product. |
| 2011-01-24 | RTL-to-GDSII reference flow optimised for 32/28nm RTL-to-GDSII reference flow optimised for 32/28nm |
| 2010-10-28 | Atrenta, TSMC join forces on synthesisable IP Atrenta Inc. and Taiwan Semiconductor Manufacturing Co. Ltd are cooperating to improve the quality of delivered synthesisable IP using Atrenta's SpyGlass platform. |
| 2010-10-08 | GN ReSound chooses Magma Design's Talus system GN ReSound chooses Magma Design's Talus system |
| 2010-06-04 | Tools bridge chip design, verification with shared database Tools bridge chip design, verification with shared database |
| 2010-05-11 | Tool enables full-chip assertion synthesis EDA start-up NextOp rolls out initial product, dubbed BugScope, a full-chip assertion synthesis product that automatically generate functional coverage properties from testbench and RTL. |
| 2010-03-01 | Approaching RTL implementation with chip synthesis Approaching RTL implementation with chip synthesis |
| 2009-09-02 | RTL power tool packs sequential analysis RTL power tool packs sequential analysis |
| 2009-06-19 | Hardware design needs hardware design languages Hardware design needs hardware design languages |
| 2009-04-29 | Talus IC implementation system supports CPF Talus becomes the first RTL-to-GDSII flow to support both the CPF and the Unified Power Format. |
| 2009-04-27 | FPGA start-up Achronix defying gravity FPGA start-up Achronix has the technology and financial stability to weather the current downturn, according to its CEO. |
| 2009-04-16 | Full-chip synthesis tool for advanced ICs upgraded Magma Design Automation Inc. has unveiled an upgraded version of Talus Design. |
| 2009-03-18 | Design system accelerates chip development Design system accelerates chip development |
| 2009-03-18 | IP devt, FPGA prototyping with SystemC/TLM Here's a design flow that starts with highly abstracted models to cycle RTL models of IP. |
| 2009-03-02 | Jasper launches new verification tools Jasper Design Automation said it is automating IC design verification routines with a new suite of tools. |
| 2009-03-02 | C-level functional qualification tool debuts Certess' functional qualification software product targets companies developing SoCs or integrating IP blocks using C. |
| 2009-01-21 | Formal verification tools roll for beginners OneSpin has amended its software and packaged it in a way that supports a step-by-step approach for beginners. |
| 2009-01-13 | Measure quality in semiconductor IP Here's an approach for communicating design intent and measuring IP quality that's rooted in how design is done. |
| 2008-11-26 | Implement two-dimensional rank order filter Here's a reference design that includes the RTL VHDL implementation of an efficient sorting algorithm. |
| 2008-10-24 | Sequence enhances power analysis tool Sequence Design has added "timing-aware" RTL power analysis feature to its PowerTheatre power analysis and prototyping tool. |
| 2008-09-19 | Breaking the gigahertz speed barrier This paper emphasises the collaborative efforts of MIPS Technologies and Synopsys that resulted in an automated RTL-to-GDSII flow. |
| 2006-06-02 | Automated video algorithm implementation The article presents an overview of a C-based design flow that enables designers to generate high-quality hardware for video algorithms. A video line filter example is used to illustrate techniques for coding video algorithms. |
| 2006-04-19 | Building reliable FPGA memory interface controllers This how-to article discusses various memory interface controller design challenges and the use of MIG to build a complete memory interface solution for your own application on a Virtex-4 FPGA. |
| 2005-05-19 | Bridging the system to RTL continuum Bridging the system to RTL continuum |
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