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2012-05-16 Cadence flow lowers n/w flow processor power
Cadence Encounter RTL-to-GDSII flow enables a boost in performance as well as reduction in power consumption on the Netronome's low-power 'green' SoCs.
2012-03-09 Cadence digital flow accelerates 20nm design
Cadence's latest RTL-to-GDSII design, implementation and signoff flow enables efficient power-performance-area trade-offs that support complex designs at advanced process nodes.
2011-01-24 RTL-to-GDSII reference flow optimised for 32/28nm
RTL-to-GDSII reference flow optimised for 32/28nm
2009-06-01 Talus 1.1 delivers fast timing closure
Magma has released Talus 1.1 that it says delivers the fastest timing closure on the most complex IC designs.
2009-04-29 Talus IC implementation system supports CPF
Talus becomes the first RTL-to-GDSII flow to support both the CPF and the Unified Power Format.
2009-03-18 Design system accelerates chip development
Lynx is optimised for Synopsys' Galaxy Design Platform and is configurable to incorporate third-party technology.
2008-09-19 Breaking the gigahertz speed barrier
This paper emphasises the collaborative efforts of MIPS Technologies and Synopsys that resulted in an automated RTL-to-GDSII flow.
2007-03-12 Total Power Optimization in RTL-to-GDSII Implementation Flow
Total Power Optimization in RTL-to-GDSII Implementation Flow
2007-07-09 Low power design specification from RTL to GDSII
Low power design specification from RTL to GDSII
2007-06-27 TSMC qualifies Magma Quartz tech for nanometre designs
With Quartz RC and the Magma Blast and Talus RTL-to-GDSII systems qualified by TSMC, designers can address new variables prevalent in 65nm, 90nm and 130nm designs to deliver the required level of accuracy.
2007-03-15 Cadence solution enables Taiwan's first 65nm IC design
Cadence Design announced that Global Unichip was the first Taiwan-based design company to complete a successful tape-out of a 65nm device with the use of Cadence Low-Power Solution and SoC Encounter GXL RTL-to-GDSII system.
2006-09-07 Synopsys, SMIC jointly develop ref design flow 3.0
Synopsys Inc. and SMIC have jointly developed and deployed reference design flow 3.0.
2006-07-21 Synopsys delivers 65nm ref flow for common platform initiative
Synopsys Inc. has announced availability of its extended RTL-to-GDSII low-power reference design flow for the latest 65-nanometer (nm) process offered by the IBM.
2006-05-26 Dongbu, Cadence develop reference flow for RTL to GDSII
Dongbu, Cadence develop reference flow for RTL to GDSII
2006-04-18 Synopsys offers RTL-to-GDSII design system
Synopsys offers RTL-to-GDSII design system
2006-03-07 Synopsys offers RTL-to-GDSII ref design for 90nm process
Synopsys offers RTL-to-GDSII ref design for 90nm process
2005-11-07 DongbuAnam, Synopsys develop 130-nm reference flow
Korean wafer foundry DongbuAnam Semiconductor Inc. and EDA giant Synopsys Inc. have jointly developed a reference flow for DongbuAnam's 130nm process, the companies said Friday (Nov. 4).
2005-11-21 SMIC, Magma offering RTL-to-GDSII flow for 130nm SoCs
SMIC, Magma offering RTL-to-GDSII flow for 130nm SoCs
2004-02-02 Choosing the right design flow model with integrated architecture
Users of ASIC, COT and COPD models are finding that flows based on an integrated RTL-to-GDSII system can offer additional benefits when fully leveraged.
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Clive Maxfield Strange modes of transport and other "stuff"

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