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| 2012-05-23 | Uniquify becomes TSMC DCA partner In order to support TSMC's customers, Uniquify provides SoC integration, interface IP and manufacturing service. |
| 2012-05-10 | Address power concerns using HLS High-level synthesis may be used to make high-level architectural decisions based on practical data while creating high-quality design implementations. |
| 2012-04-09 | Designing NAND flash controller with high-level synthesis Designing NAND flash controller with high-level synthesis |
| 2012-01-25 | How formal MDV can take out IP integration uncertainty Find out how the formal metric-driven verification methodology and technologies can eliminate integration uncertainty through the automatic generation of Accellera-defined coverage metrics. |
| 2011-04-11 | Facilitating at-speed test at RTL (Part 1) Lear how to facilitate at-speed test at the register transfer level. |
| 2009-09-02 | RTL power tool packs sequential analysis Calypto Design Systems Inc. has developed what it claims to be the most accurate register-transfer level (RTL) power analysis capability by applying its patented sequential analysis technology. |
| 2009-03-18 | IP devt, FPGA prototyping with SystemC/TLM Here's a design flow that starts with highly abstracted models to cycle RTL models of IP. |
| 2009-03-05 | Behavioural design for low-power silicon Know how to use high level synthesis to reduce power consumption and improve other aspects of circuit quality. |
| 2009-02-09 | Boost functional verification with SLEC SLEC has the capability to formally verify RTL implementations against a specification in C/C++ or System C. |
| 2007-06-18 | Industry tackles approach to DFM, DFY issues Experts from chip, EDA and foundry companies ask whether it's better to deal with DFM and DFY issues at tape-out or minister to the design starting at the register transfer level. |
| 2005-08-26 | Open-Silicon joins TSMC's design center alliance Fabless ASIC supplier Open-Silicon Inc. has joined Taiwan Semiconductor Mfg Co. Ltd (TSMC)'s design center alliance program. |
| 2001-01-01 | Test coverage enhancements at the register transfer level Test coverage enhancements at the register transfer level |
| 2001-06-01 | Extraction method verifies IP functions To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process. |
| 2005-03-16 | Transaction-based simulation using SystemC/SCV Learn how SystemC/SCV speeds up simulation and verification cycles to provide overall project cycle with better quality results |
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