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| 2011-03-11 | EFEC IP cores target 100G applications Altera unveils the EFEC IP cores optimised for Stratix IV and V series FPGAs and designed for 100G applications such as metro and long-haul optical networks (OTN). |
| 2011-02-11 | FPGAs aimed at 100G wireline applications Altera Corp. has completed interoperability tests between its Stratix IV GT FPGA and MoSys' Bandwidth Engine device in a serial memory application, providing designers of 100G wireline applications with a high-bandwidth memory solution. |
| 2010-06-16 | Highest density FPGAs pack 820K logic elements Altera Corp. has started rolling out Stratix IV E EP4SE820 FPGA, the highest density member of its 40nm Stratix IV FPGA family featuring 820K logic elements, 23.1Mbit embedded memory and 960 18x18 multipliers. |
| 2010-03-11 | Interlaken IOT ratifies Altera's Stratix IV FPGAs Interlaken IOT ratifies Altera's Stratix IV FPGAs |
| 2010-01-05 | Manual placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT devices Manual placement of CMU PLLs and ATX PLLs in Stratix IV GX and GT devices |
| 2010-01-05 | Achieving timing closure in basic (PMA direct) functional mode This application note describes two methods to achieve timing closure for designs that use transceivers in Basic (PMA Direct) mode at higher data rates for Altera's Stratix IV GX or Stratix IV GT FPGAs. |
| 2010-01-04 | Implementing the interlaken protocol in Stratix IV transceivers Implementing the interlaken protocol in Stratix IV transceivers |
| 2009-12-29 | Designing power isolation filters with ferrite beads for Altera FPGAs This application note provides guidelines for designing ferrite bead filter networks to isolate shared power rails of Stratix IV FPGAs. |
| 2009-12-30 | Implementing the scalable Serdes framer interface (SFI-S) protocol in Stratix IV GT devices Implementing the scalable Serdes framer interface (SFI-S) protocol in Stratix IV GT devices |
| 2009-12-29 | Implementing the Serdes Framer interface level 5 (SFI-5.1) protocol in Stratix IV devices Implementing the Serdes Framer interface level 5 (SFI-5.1) protocol in Stratix IV devices |
| 2009-12-23 | Recommended protocol configurations for Stratix IV GX FPGAs Recommended protocol configurations for Stratix IV GX FPGAs |
| 2009-12-21 | Stratix III-to-Stratix IV E cross-family migration guidelines Stratix III-to-Stratix IV E cross-family migration guidelines |
| 2009-09-16 | 40nm FPGA tailored for high-end digital apps Altera Corp. has extended its high-end density range of its 40nm Stratix IV E FPGAs to 820K logic elements (LEs). |
| 2009-06-08 | Altera rolls out Stratix IV GX FPGA devt kit Altera rolls out Stratix IV GX FPGA devt kit |
| 2009-02-12 | FPGAs with integrated 11.3-Gbps transceivers Altera's Stratix IV GT and Arria II GX 40-nm FPGA families join Stratix IV GX FPGAs and HardCopy IV GX ASICs. |
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