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| 2010-06-29 | MindTree adopts Mentor's verification platform MindTree has joined Mentor Graphics' Questa Vanguard Programme and adopted a verification flow based on Mentor's Questa functional verification platform and the Open Verification Methodology. |
| 2009-06-05 | Memory model generator cuts verification time eInfochips has announced the availability of a DDR2 SDRAM SystemVerilog Memory Model Generator. |
| 2008-12-09 | Open source OVM solution rolls The Cadence solution lets users run both OVM and VMM VIP within a single OVM environment |
| 2008-12-08 | Open-source SystemVerilog solution rolls for OVM Open-source SystemVerilog solution rolls for OVM |
| 2008-10-17 | Verification IP is fully-OVM compliant Silicon Interfaces introduced their GEMAC SystemVerilog OVM-compliant OVC VIP. |
| 2008-10-16 | Grasp SystemVerilog testbench debug, analysis Grasp SystemVerilog testbench debug, analysis |
| 2008-08-04 | OVM quickly find bugs in IP design KPIT Cummins has successfully used the class-based Open Verification Methodology to develop CAN verification IP. |
| 2005-05-18 | MATLAB: The sleeper ESL hit The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow. |
| 2005-05-18 | MATLAB: The sleeper ESL hit The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow. |
| 2006-09-04 | SystemVerilog reference verification methodology: VMM adoption SystemVerilog reference verification methodology: VMM adoption |
| 2008-06-10 | EInfochips debuts verification IP EInfochips Ltd has unveiled what it calls the first SystemVerilog verification IP that complies with the OVM and AVM 3.0. |
| 2008-02-19 | Cadence, Mentor upgrade OVM source-code library Cadence Design Systems and Mentor Graphics have announced an enhanced release of the source-code library and user documentation for the OVM, claimed to be the industry's first open, interoperable SystemVerilog verification methodology. |
| 2008-01-24 | TBX eases co-verification for embedded systems Mentor has announced what it claims as the industry's only commercially proven RTL-accurate virtual emulation capability that eliminates the traditional barriers of adopting hardware in-circuit emulation for system-level integration. |
| 2008-01-11 | Cadence, Mentor launch OVM Cadence and Mentor have launched the OVM based on IEEE Std. 1800-2005 SystemVerilog standard, which they claim as the industry's first open, language interoperable, SystemVerilog verification methodology. |
| 2007-10-16 | Cadence, Mentor promote OVM Cadence and Mentor have joined forces to offer an OVM rooted in IEEE 1800 with transaction-level modeling support that is interoperable among EDA tools and that supports interoperable VIP. |
| 2007-10-10 | Oki adopts Synopsys' SystemVerilog for verification Oki adopts Synopsys' SystemVerilog for verification |
| 2007-08-23 | Synopsis missing in OVM initiative Despite Synopsis' role in creation of SystemVerilog, Cadence and Mentor made no attempt to invite Synopsis to join and extend the benefits of the OVM initiative worldwide. |
| 2007-08-22 | Cadence, Mentor team to standardise OVM Cadence and Mentor Graphics have partnered to standardise on OVM that promises to deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability. |
| 2007-08-14 | Boost productivity with ESL techniques The increased complexity that comes with 90nm and smaller geometries have led to a myriad of severe challenges, including HW/SW co-design, power management and verification. An ESL methodology offers a viable solution to these challenges. |
| 2007-03-23 | Planning the verification process with SystemVerilog Planning the verification process with SystemVerilog |
| 2007-02-21 | SystemVerilog fails to deliver on design SystemVerilog fails to deliver on design |
| 2007-01-24 | IC emulator handles 10 crore gates at 20MHz EVE SA has claimed to have developed the largest and fastest IC emulation product to date. ZeBu-XXL handles up to 100 million gates at up to 20MHz. |
| 2007-01-10 | Renesas adopts Synopsys' VCS verification, VMM method Synopsys Inc. has announced that Renesas Technology Corp. has adopted the VCS functional verification solution and VMM methodology to verify its critical SuperHyway bus on-chip interconnect infrastructure. |
| 2006-11-22 | Freescale, Synopsys sign EDA verification agreement Freescale Semiconductor Inc. and Synopsys Inc. have signed an agreement for Freescale's use of the latter's electronic design automation software for the functional verification of complex semiconductor designs. |
| 2006-10-04 | Yogitech announces OCP verification component Yogitech SPA, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol UVC. |
| 2006-09-21 | Synopsys donates power management tech to EDA org Synopsys Inc. has donated power management technology to Accellera. The donation includes power management commands, SystemVerilog constructs, VHDL constructs and the Switching Activity Interchange Format. |
| 2006-06-01 | IEEE approves Cadence's 'e' language The IEEE has approved Cadence Design Systems Inc.'s "e" verification language, making it an open standard that anyone can use or support. |
| 2006-05-11 | Mentor enhances verification options for Questa users Mentor Graphics Corp. has announced a partnership with industry-leading companies to enhance the verification options for Questa users. |
| 2006-04-19 | Vendors support SystemVerilog synthesis Vendors support SystemVerilog synthesis |
| 2006-03-27 | Synopsys announces first Verification Library Synopsys has announced its VCS Verification Library, which is first to support testbenches created using IEEE Std 1800-2005 SystemVerilog and the coverage-driven methodology. |
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