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| 2012-05-07 | Tensilica's India facility gets expansion, to hire more employees Tensilica's India facility gets expansion, to hire more employees |
| 2012-04-24 | Tensilica expands R&D centre in Pune Tensilica expands R&D centre in Pune |
| 2012-04-19 | Renesas licenses Tensilica's DSP IP core Renesas licenses Tensilica's DSP IP core |
| 2012-01-11 | Audio/voice DSPs speed smartphone algorithms Tensilica Inc. HiFi 3 audio/voice DSP IP core is suited for SoCs in home entertainment systems and smartphones. |
| 2011-03-31 | DSP core targets cellular base band Aimed at cellular base bands, Tensilica's Xtensa LX4 boasts lower power and a smaller footprint, reaching speeds of more than 1GHz in a high-performance 45nm process with an area of only 0.044mm2. |
| 2011-02-09 | Reference architecture targets dataplane processors Tensilica customers may now evaluate the optimised programmable dataplane processing units of its Atlas Reference Architecture that supports the 3GPP LTE, HSPA+ and WiMAX standards. |
| 2010-12-10 | Math library eases porting of software codecs Tensilica presents the NatureDSP Math library is a collection of signal processing routines used when implementing typical digital signal processing functions which utilise the HiFi audio DSP architecture. |
| 2010-09-27 | Tensilica gets funds from Fujitsu Tensilica gets funds from Fujitsu |
| 2010-09-20 | AppliedMicro taps Tensilica for high-throughput project AppliedMicro taps Tensilica for high-throughput project |
| 2010-08-24 | KPIT Cummins partners Tensilica as SoC design centre KPIT Cummins partners Tensilica as SoC design centre |
| 2010-07-13 | Beefed up HiFi Audio codec lib offers FLAC decoder Tensilica is upgrading its HiFi Audio DSP family of IP core software library with the addition of the increasingly popular Free Lossless Audio Codec (FLAC) decoder. |
| 2010-03-26 | Controllers offer fast clock speed in smaller area Tensilica Inc. unveils its third generation of Diamond Standard controllers that ups clock speed by up to 15 per cent, cuts die are by up to 20 per cent and lessens power consumption by up to 15 per cent. |
| 2010-02-04 | Low-power DSP core targets portable apps Tensilica has developed the HiFi EP, a superset of the HiFi 2 architecture which minimises power consumption making it well-suited for low-power portable applications. |
| 2009-12-22 | MIPS, Tensilica team on Android platform-based SoC MIPS, Tensilica team on Android platform-based SoC |
| 2009-11-06 | Processor packs wide pre-verified DSP options Tensilica launched the Xtensa LX3 high-performance dataplane processor (DPU) core optimised for DSP and control in the SoC dataplane. |
| 2009-09-03 | DSP engine packs dual 16bit MAC units Tensilica Inc. has launched the ConnX D2 16bit dual-MAC (multiply accumulate) DSP engine for its proven Xtensa LX dataplane processor cores for SoC designs. |
| 2009-06-24 | DSPs suit 3G, 4G SoC designs Tensilica Inc. has launched the ConnX family of DSPs for 3G and 4G system-on-chip designs. |
| 2009-01-19 | Audio DSPs support RealAudio decoders Tensilica has ported the RealAudio 8, 9 and 10 decoders from RealNetworks to the HiFi 2 Audio DSP. |
| 2008-10-06 | Tensilica joins SpyLinks alliance program Tensilica joins SpyLinks alliance program |
| 2008-10-03 | Implementing data encryption standard This document provides a software implementation of the DES algorithm using Xtensa processor extensions. |
| 2008-10-03 | Speeding up MPEG-4 video decoding with an Xtensa processor This document demonstrates how to accelerate major parts of video decoding using TIE. |
| 2008-10-03 | Fast Fourier Transform for Xtensa processor This document aims to show the results and design methodology for a DSP app on Xtensa microprocessor using FFT. |
| 2008-10-03 | Implement fast IP packet forwarding This application note explains how to configure an Xtensa processor to achieve fast IP packet forwarding. |
| 2008-10-03 | Implementing fast IP packet classification This document explains how to achieve fast IP packet classification with a configurable processor. |
| 2008-10-01 | Turbo coding on configurable processors Xtensa processors can be optimised to handle the signal processing demands of supporting turbo decoding. |
| 2008-09-29 | Ways of extending JTAG.v module's functionality This application note discusses a couple of possible extensions to the jtag.v module. |
| 2008-09-29 | System software example for audio reference design This document discusses a system software example that performs back-to-back audio stream decoding of audio formats. |
| 2008-09-29 | Building Xtensa-based emulation system on Xilinx FPGA This application note describes how to map an Xtensa or Diamond core to an FPGA with a minimal on-chip system. |
| 2008-09-29 | Speeding up double-precision floating point emulation This document provides a small set of TIE instructions and states for accelerating double-precision emulation. |
| 2008-09-26 | Advanced Encryption Standard on configurable processors Learn about the AES cipher and illustrates how configurable processors speed up encryption and decryption. |
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