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| 2012-05-07 | Employ modelling for power integrity simulation in 3D-IC design Learn how analysis based on a chip macro-model can yield the same results as concurrent full-chip analysis, resulting in significant runtime benefits. |
| 2012-04-30 | GlobalFoundries announces 3D chip stacking at 20nm At its Fab 8 campus, GlobalFoundries is installing a special set of semiconductor production tools to create through-silicon vias in 20nm node semiconductor wafers. |
| 2012-03-09 | Applied Materials, IME open 3D chip packaging lab The centre is expected to help accelerate the development and adoption of 3D packaging technology globally. |
| 2011-06-20 | 3D IC opens new doors for the wireless market Find out how EDA tools and infrastructure will emerge to build 3D ICs with through-silicon vias. |
| 2010-07-19 | Engineers discuss 3D chip standard A group of about 60 engineers gathered at a Semicon West 2010 in San Francisco took the first crack at outlining standards needed for 3D silicon chips including address design, yield and cost problems. |
| 2010-06-23 | Elpida, PTI, UMC push 3D IC integration for 28nm Elpida Memory Inc., Powertech Technology Inc. (PTI), and United Microelectronics Corp. have reached a three-way cooperation to advance 3D IC integration technologies for advanced processes including 28nm. |
| 2010-06-18 | 3D TSV chips still pre-mature Some experts from VLSI Research after attending the International Interconnect Technology Conference (IITC) have concluded that 3D chips based on through-silicon-vias (TSV) are not ready for prime time. |
| 2010-03-15 | Alchimer opens 3D TSV tech facility in South Korea Alchimer S.A. has opened a new applications and development facility in Seoul, South Korea, for demonstration of its 3D TSV processes on 300mm wafers. |
| 2010-03-12 | IMEC, Synopsys to research on 3D stacked ICs Synopsys Inc. and IMEC have formed a collaborative research team to accelerate the development of 3D stacked IC technologies. |
| 2009-10-19 | ITRI, Applied Materials unite for 3D IC Applied and ITRI are collaborating to work together as members of the Stacked-System and Application Consortium |
| 2009-07-21 | EVG, Applied partner on 3D wafer bonding EV Group (EVG) and Applied Materials Inc. are collaborating to develop wafer bonding processes for the manufacture of through-silicon vias (TSVs) in 3D IC packaging applications. |
| 2008-12-04 | Applied helps accelerate TSV adoption Applied Materials is leading a major effort to enable the widespread adoption of through-silicon vias. |
| 2008-10-09 | Stacked microprocessor system promises enhanced performance A new approach to cooling chips may be the most efficient heat dissipation that is possible for stacked microprocessors. |
| 2008-09-01 | 3D-TSVs usher in packaging revolution 3D-TSV wafers could account for more than 6 per cent of the total semiconductor industry by 2015. |
| 2008-06-09 | 3D buzz centres on TSVs Through-silicon vias technology continues to generate steam. |
| 2007-06-01 | IBM adds a milestone to 3D packaging The first commercial device to be sampled by IBM Corp. this year, to make direct metal connections between chips, promises advances in performance, power and cost for a broad array of systems. |
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