What does VHDL stand for?
| VHDL or VHSIC Hardware Description Language is a hardware description language used to design electronic systems at the component, board and system level. |
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| 2011-06-06 | Get the most out of IDEs for hardware design and verification Read about the current growth and future prospects of IDEs in hardware verification, as well as its implications for hardware design. |
| 2009-05-22 | IDE for VHDL boosts design productivity IDE for VHDL boosts design productivity |
| 2009-04-13 | FIFO Dipstick with Warp2 VHDL, CY7C371 FIFO Dipstick with Warp2 VHDL, CY7C371 |
| 2008-12-11 | Aldec rolls out ALINT 2008.10 Aldec Inc. says ALINT reduces risk when developing complex multi-million gate ASICs. |
| 2008-11-26 | Implement two-dimensional rank order filter Here's a reference design that includes the RTL VHDL implementation of an efficient sorting algorithm. |
| 2008-11-12 | Making designs 50% smaller Here's a design technique that can make a difference in the size and the performance of your FPGA design. |
| 2008-04-01 | Speed up your RTOS synthesis To investigate the use of software synthesis technology, engineers set out to use a software synthesis tool to generate an embedded RTOS. Performance measurements were also taken to see how well the synthesised system worked. |
| 2005-01-02 | Back to the language roots It's not time for the revolution yet. Traditional hardware-description languages have specific features that make them superior to software programming languages; although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL. |
| 2005-01-01 | Compiling software to gates Are VHDL and Verilog past their prime, soon to be replaced by C-like design languages such as System C, Handel-C, and others? Professor Ian Page thinks a change is at hand. |
| 2007-12-24 | Aldec introduces multi-threaded VHDL compilation Aldec introduces multi-threaded VHDL compilation |
| 2007-09-20 | Devt kit for customisable ARM9-based MCUs debuts Atmel has introduced its FPGA devt kit that allows the simultaneous development and emulation of both the ARM9 software and FPGA Verilog/VHDL designs. |
| 2007-01-24 | IC emulator handles 10 crore gates at 20MHz EVE SA has claimed to have developed the largest and fastest IC emulation product to date. ZeBu-XXL handles up to 100 million gates at up to 20MHz. |
| 2006-11-16 | Revised VHDL spec boosts IP security Revised VHDL spec boosts IP security |
| 2006-10-04 | Yogitech announces OCP verification component Yogitech SPA, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol UVC. |
| 2006-09-21 | Synopsys donates power management tech to EDA org Synopsys Inc. has donated power management technology to Accellera. The donation includes power management commands, SystemVerilog constructs, VHDL constructs and the Switching Activity Interchange Format. |
| 2006-07-26 | Accellera approves new VHDL standard Accellera approves new VHDL standard |
| 2006-04-28 | VDA VHDL-AMS models run in Synopsys' simulator VDA VHDL-AMS models run in Synopsys' simulator |
| 2006-02-03 | Engineer designs tool to generate logic specs After working in labs designing fault-tolerant flight-control systems, Dave McFarland came to realise that there's no good way to specify logic and look at all the possible combinations. So he built a tool to handle the job. |
| 2002-10-11 | ispLSI 8000V Family VHDL Code Examples ispLSI 8000V Family VHDL Code Examples |
| 2001-03-21 | FIFO Dipstick using Warp2 VHDL and the CY7C371 FIFO Dipstick using Warp2 VHDL and the CY7C371 |
| 2000-12-01 | IBIS and SPICE: Modeling languages for the demanding EDA industry This technical article summarizes IBIS and SPICE modeling language, looks at some of the new IBIS developments and then takes a look at the future. |
| 2005-08-29 | ESL tool tames one tough task: On-chip register design Blueprint, an electronic system level tool from Denali Software, automatically generates and manages the vast number of on-chip control registers that users no doubt find themselves juggling. |
| 2005-09-01 | Sub-$200 tools power 'farms' for verification Stanley Hyduke sees a not-so-distant future for the semiconductor industry in which companies are running thousands of simultaneous simulations to cope with the verification bottleneck. |
| 2005-10-03 | Denali spreads new word in ESL mart With a missionary zeal to establish standards and design methodologies, Denali Software leaps into the ESL market. |
| 2000-12-01 | The advantage of using logic BIST for ASIC designs This technical paper reveals the advantage of using logic BIST for ASIC designs. |
| 2001-01-01 | A faster way to run Reed Solomon decoders This technology news describes the new Reed-Solomon (RS) decoder architecture that can process multiple symbols per clock cycle. |
| 2001-03-01 | Complex designs demand greater attention to data management Complex designs generate huge amounts of data. A data-centric methodology addresses the data management challenge by employing a design-centric rather than a tool-centric methodology. |
| 2001-03-01 | One approach for debugging of modified designs Two engineers describe a methodology of comparing old designs to new designs in order to validate the new one. |
| 2001-03-01 | Peripheral model makes dual run With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process. |
| 2001-03-19 | The FLASH370i family of CPLDs and designing with Warp2 This application note covers the following topics: a general discussion of complex programmable logic devices (CPLDs); an overview of the FLASH370i family of CPLDs; and using the Warp2 VHDL Compiler for the FLASH370i family. |
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