What is Verilog?
| The Verilog HDL is an industry-accepted standard hardware description language commonly used to design ASICs and FPGAs. The designers of Verilog wanted to design a language based on the C programming language so that it would be familiar to engineers and readily accepted. In practice, it bears only a vague resemblance to C. |
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| 2011-06-06 | Get the most out of IDEs for hardware design and verification Read about the current growth and future prospects of IDEs in hardware verification, as well as its implications for hardware design. |
| 2011-04-01 | Synopsys leverages verification via cloud Synopsys Inc. plans to leverage the power of cloud computing by offering verification services using thousands of computers to run simulations on customer designs. |
| 2011-02-16 | Interfacing QDR II SRAM devices with Virtex-6 FPGAs Here's a Verilog reference design that has been simulated, synthesized, and verified on hardware using Virtex-6 FPGAs and QDR II SRAM two-word burst devices. |
| 2010-12-22 | Cortex-M0 processor designed for curriculum, research ARM reveals the availability of ARM Cortex-M0 processor via the ARM DesignStart online IP portal that aims to accelerate the proliferation of the technology in university curriculum and research projects. |
| 2010-01-22 | 64bit simulator runs 10x faster without FPGA tools From SynaptiCAD comes the first 64bit Linux version of VeriLogger Extreme, a Verilog simulation and debug environment which is 30 per cent faster than the 32bit version. |
| 2008-12-29 | Improve SI in high density FPGA-based designs Know how to generate a Verilog test code, and detect assembly and fabrication-related faults. |
| 2008-12-11 | Aldec rolls out ALINT 2008.10 Aldec Inc. says ALINT reduces risk when developing complex multi-million gate ASICs. |
| 2008-11-12 | Making designs 50% smaller Here's a design technique that can make a difference in the size and the performance of your FPGA design. |
| 2008-08-26 | Standard improves AMS design Accellera announced that its Board of Directors and Technical Committee members approved Verilog-AMS 2.3. |
| 2008-06-25 | Software detects clock violations Aldec announces ALINT 2008.06 with new enhancements including the addition of 15 new STARC rules. |
| 2003-08-01 | The C programmer's guide to Verilog The C programmer's guide to Verilog |
| 2005-01-02 | Back to the language roots It's not time for the revolution yet. Traditional hardware-description languages have specific features that make them superior to software programming languages; although SystemC has its place in the hardware-design process, it still can't compete with Verilog and VHDL. |
| 2005-01-01 | Compiling software to gates Are VHDL and Verilog past their prime, soon to be replaced by C-like design languages such as System C, Handel-C, and others? Professor Ian Page thinks a change is at hand. |
| 2007-09-20 | Devt kit for customisable ARM9-based MCUs debuts Atmel has introduced its FPGA devt kit that allows the simultaneous development and emulation of both the ARM9 software and FPGA Verilog/VHDL designs. |
| 2007-01-24 | IC emulator handles 10 crore gates at 20MHz EVE SA has claimed to have developed the largest and fastest IC emulation product to date. ZeBu-XXL handles up to 100 million gates at up to 20MHz. |
| 2007-01-10 | C-to-RTL compiler to generate full-chip designs CebaTech Inc. plans to roll out the C2R Compiler, a C-to-RTL compiler that promises to generate full-chip designs. |
| 2007-01-09 | Verilog simulator offers faster RTL simulation Verilog simulator offers faster RTL simulation |
| 2006-11-16 | Revised VHDL spec boosts IP security The Accellera standards organisation has approved a revised version of the VHDL specification, marking a huge step forward for the design language. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for IP encryption. |
| 2006-10-31 | Cadence, Source III collaborate on test validation Cadence Design Systems Inc. and Source III Inc. are collaborating to enable improved test validation and faster test conversion for enhanced chip quality. |
| 2006-10-04 | Yogitech announces OCP verification component Yogitech SPA, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol UVC. |
| 2001-01-01 | EDA platform benchmark: The desktop FPGA design flow This article evaluates the system requirements of your desktop against typical FPGA designs you would encounter. |
| 2005-08-29 | ESL tool tames one tough task: On-chip register design Blueprint, an electronic system level tool from Denali Software, automatically generates and manages the vast number of on-chip control registers that users no doubt find themselves juggling. |
| 2005-08-29 | Accellera approves open verification library standard Open Verification Library (OVL) 1.0 has been approved by EDA standards organization Accellera's board of directors |
| 2005-09-01 | Sub-$200 tools power 'farms' for verification Stanley Hyduke sees a not-so-distant future for the semiconductor industry in which companies are running thousands of simultaneous simulations to cope with the verification bottleneck. |
| 2005-10-03 | Denali spreads new word in ESL mart With a missionary zeal to establish standards and design methodologies, Denali Software leaps into the ESL market. |
| 2001-02-01 | Behavioral modeling accelerates for OEM requirements This technical article describes the high-level behavioral modeling that can speed-up design along the road to tapeout by identifying architectural opportunities and pitfalls. |
| 2001-03-01 | One approach for debugging of modified designs Two engineers describe a methodology of comparing old designs to new designs in order to validate the new one. |
| 2001-03-20 | Method to instantiate and use a core in Warp with Cypress CPLDs This application note describes in detail how customers can incorporate cores in their system-level designs. It contains a detailed description of the steps required to instantiate VIF files in both VHDL and Verilog designs. |
| 2001-04-15 | Speed enhancements for Model Tech upgrades This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support. |
| 2001-06-01 | Formal verification of an MPEG decoder chip This article outlines the application of formal verification through model checking of the control unit in a DVD decoder chip. |
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