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| 2010-08-16 | IP portfolio broadens SoC infrastructure solution Virage Logic Corp. broadens its SoC infrastructure IP portfolio with the Integra product line based on proven technology acquired from NXP last year. |
| 2010-07-30 | Dual-core processor suits HD audio apps Virage Logic Corp. rolls out the ARC Sound AS221BD dual-core processor for High Definition (HD) Audio SoCs offering a complete HD sound-to-silicon solution that includes Blu-ray software. |
| 2010-06-16 | Synopsys to pay Rs.1,454.58 crore for Virage Logic Synopsys to pay Rs.1,454.58 crore for Virage Logic |
| 2010-04-19 | Virage Logics has sub-systems on its radar Virage Logics has sub-systems on its radar |
| 2010-02-23 | Open-Silicon, Virage team on low-power silicon Open-Silicon, Virage team on low-power silicon |
| 2010-01-18 | Netherlands R&D centre to develop CMOS-based products It has been established as a result of Virage Logic's recent acquisition of NXP's horizontal advanced CMOS intellectual property (IP) rights and certain engineering talent and equipment. |
| 2009-10-14 | NXP transfers CMOS IP to Virage Logic NXP transfers CMOS IP to Virage Logic |
| 2009-08-20 | Virage expands IP portfolio with ARC buyout Virage expands IP portfolio with ARC buyout |
| 2009-05-25 | Virage, eMemory roll out embedded NVM tech Virage, eMemory roll out embedded NVM tech |
| 2009-03-04 | NEC gets Virage Logic as IP partner for 40nm NEC gets Virage Logic as IP partner for 40nm |
| 2009-01-29 | AMD, Virage Logic announce collaboration AMD, Virage Logic announce collaboration |
| 2008-12-05 | Virage offers $10M to acquire LogicVision Virage offers $10M to acquire LogicVision |
| 2008-10-01 | NextIO, Virage Logic to advance process node NextIO, Virage Logic to advance process node |
| 2008-09-11 | Analog Devices licenses Aeon NVM tech Analog Devices has licensed Virage Logic's Aeon embedded NVM for use in analogue and mixed-signal products. |
| 2008-05-01 | New SiWare products roll out Virage Logic has released the latest memory compilers and logic libraries for TSMC's 40-nanometer (nm) process. |
| 2008-04-30 | CSR expands use of Virage Logic IP CSR expands use of Virage Logic IP |
| 2008-04-29 | DRAM controller ups efficiency by 20% Virage Logic has announced a DDR memory controller that can boost efficiency by 20 per cent while still maintaining low-power. |
| 2007-11-12 | ARM pulls back curtain on 32nm physical IP initiative Looking to get a jump on rivals like TSMC and Virage Logic, ARM has pulled back the curtain on its 32nm initiative for physical IP, despite warning that the dreaded shift to 32nm will be an expensive and risky proposition. |
| 2007-10-25 | Virage Logic expands its 65nm IP products Virage Logic expands its 65nm IP products |
| 2007-02-01 | Virage Logic intros non-volatile memory for security apps Virage Logic intros non-volatile memory for security apps |
| 2007-01-25 | Virage Logic joins Si2's Low Power Coalition Virage Logic joins Si2's Low Power Coalition |
| 2006-11-30 | Open-Silicon, MIPS to offer processor core Open-Silicon has signed a deal with MIPS Technologies to offer the latter's MIPS32 24Kc Pro processor core for use in ASIC and SoC designs. The company has also licensed a 90nm IP kit that was jointly developed by MIPS Technologies and Virage Logic Corp. |
| 2006-11-22 | Open-Silicon selects MIPS' processor core for ASIC MIPS Technologies Inc. has announced that Open-Silicon Inc. has selected the MIPS32 24KEc Pro processor core to power advanced custom ASIC solutions for complex SoCs. Open-Silicon has developed a business model that simplifies IP selection and integration for ASIC designers. |
| 2006-09-25 | Virage Logic adopts Synopsys' HSPICE simulator Virage Logic adopts Synopsys' HSPICE simulator |
| 2006-07-28 | Cadence, Magma, Extreme DA to develop industry standard library format Cadence Design Systems, Magma Design Automation and Extreme DA, with support from ARM, Virage Logic Corp. and Altos Design Automation, have announced their collaboration to accelerate the creation of a standard statistical analysis library format under the Open Modelling Coalition of Si2. |
| 2006-07-05 | Sequence to host low-power design seminar in Bangalore Sequence Design is taking its low-power design seminar to Bangalore for the first time on Aug. 30, 2006. |
| 2006-01-16 | Test, repair embedded memories for higher yield Embedded repair for memories is a key manufacturing technology that can optimise yield and minimize overall test cost. |
| 2005-09-08 | MIPS, Virage joint effort provides ease of a single license MIPS, Virage joint effort provides ease of a single license |
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