What is ATPG (Automatic Test Pattern Generation)?
| The automatic creation of test patterns or "vectors" used to verify the operation of an electronic circuit. The "goodness" of a set of test vectors is based on "fault coverage" or the ability of the set of test vectors to identify any manufacturing or design defects in the circuit. |
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| 2011-10-03 | Volume diagnostics solution enhanced Synopsys Inc. unveils new capabilities in its TetraMAX ATPG and Yield Explorer, promising to decrease the time, effort and cost of deploying a volume diagnostics flow and speed-up yield ramp. |
| 2010-03-03 | Target small delay defects with ATPG Target small delay defects with ATPG |
| 2009-02-10 | Magma licenses ATPG to LogicVision Magma licenses ATPG to LogicVision |
| 2006-10-30 | Test methods identify small delay defects Here's how to improve test quality without dramatically increasing the cost of test. |
| 2008-01-16 | Achieve low-power manufacturing test The article examines the relationship between dynamic power consumption and digital circuit test. It also explores two DFT methods that take advantage of recent ATPG technology to automate the creation of low power manufacturing tests. |
| 2008-01-16 | DFM-oriented test ensures better yield A scan diagnostic flow is yield-friendly and can be effectively used to accelerate production ramp and to identify DFM sensitivities that result in systematic yield-loss mechanisms. |
| 2007-10-16 | Magma ATPG products expand DFT capabilities Magma ATPG products expand DFT capabilities |
| 2007-10-08 | Xpress tech provides compression levels exceeding 100X Mentor Graphics has announced new Xpress tech in its TestKompress ATPG product to address the industry's increasing demand for scan test compression. |
| 2007-06-01 | Testing complex systems on chip Learn about the unique test challenges of SoCs, scan techniques, advanced fault models and test compression needed to keep pattern volume and test costs minimal. |
| 2007-03-23 | Measure true ATPG performance improvements Measure true ATPG performance improvements |
| 2006-12-12 | Cadence, Advantest enter automotive testing partnership Cadence Design Systems Inc. and Advantest Corp. have announced a collaborative partnership to deliver a methodology for zero-defect testing of digital automotive electronics. This collaboration will enable faster time-to-market and more complete testing of complex digital devices for new automobiles. |
| 2006-10-31 | Cadence, Source III collaborate on test validation Cadence Design Systems Inc. and Source III Inc. are collaborating to enable improved test validation and faster test conversion for enhanced chip quality. |
| 2005-12-16 | Unified methodology enables full-chip test The article will discuss shortcomings of today's test flows and propose a unified methodology for implementing full-chip test. |
| 2000-12-01 | SoCs likely to pose heading-off test problems This technology news article describes the problems and solutions test engineers should face when confronting SoC designs. |
| 2000-12-01 | The advantage of using logic BIST for ASIC designs This technical paper reveals the advantage of using logic BIST for ASIC designs. |
| 2001-12-16 | Overcoming in-circuit testability problems This technical article describes the common testability problems encountered with in-circuit designs and the basic requirements needed to solve them. |
| 2003-04-16 | DBIST answers advanced SoC test challenges Due to the exponential growth in the time and cost to apply scan tests on sophisticated SoCs, Synopsys Inc. releases its DBIST as a key capability in its new product for advanced SoC testing, the DFT Compiler SoCBIST. |
| 2004-12-01 | Vector generation for structural testers Sizing of modern ASICs and SoCs requires an array of vectors for comprehensive testing to achieve the required quality levels. |
| 2005-05-16 | Across the flow: DFM's many faces EDA toolmakers, designers forge partnership to develop new DFM process flow |
| 2005-08-16 | DFT, DFM tests assure quality SoC design Learn the importance of design-for-manufacturability and design-for-test in ramping up advanced products in deep-submicron technologies |
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