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| 2010-05-11 | Tool enables full-chip assertion synthesis Tool enables full-chip assertion synthesis |
| 2010-04-13 | High level synthesis enables low-power design High level synthesis enables low-power design |
| 2010-03-01 | Approaching RTL implementation with chip synthesis Approaching RTL implementation with chip synthesis |
| 2009-04-16 | Full-chip synthesis tool for advanced ICs upgraded Full-chip synthesis tool for advanced ICs upgraded |
| 2009-02-27 | Clock concurrent optimisation tool launched Azuro's Rubix can deliver up to 20% increases in chip speed and dramatically slash chip time to market. |
| 2008-12-18 | Cut power consumption in Fibre Channel switch Read about power optimisation for SoCs that has been accomplished using RTL synthesis tools. |
| 2008-11-12 | Atrenta deals with ESL synthesis Atrenta deals with ESL synthesis |
| 2006-11-27 | Using fill synthesis for enhanced planarisation (1 Using fill synthesis for enhanced planarisation (1 |
| 2008-05-22 | Floorplan tool delivers predictability The Hydra is a flexible automated floorplan synthesis tool that delivers superior predictability. |
| 2007-07-11 | Cadence RTL synthesis tool targets chip-level interconnect Cadence RTL synthesis tool targets chip-level interconnect |
| 2007-02-19 | MCU integrates 8bit CPU core, voice synthesis LSI MCU integrates 8bit CPU core, voice synthesis LSI |
| 2007-02-07 | Oki launches OTP memory voice-synthesis LSI Oki launches OTP memory voice-synthesis LSI |
| 2006-12-13 | Synthesis tool suffices CMP design rules Synthesis tool suffices CMP design rules |
| 2006-01-27 | Physical synthesis tool combines flat, hierarchical design Physical synthesis tool combines flat, hierarchical design |
| 2002-01-01 | Articulating hierarchical design for SoCs The unified flow for complex designs, complete with hierarchical design capabilities, is an intuitively pleasing proposition. |
| 2002-03-16 | 'Divide and conquer' with hierarchical design This technical article describes how physical synthesis alone could not present a complete solution to the challenges of advanced chip design. Therefore, as an alternative, designs must be subdivided into manageable blocks. |
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