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| 2010-08-13 | Design suite enhances FPGA partial reconfiguration Xilinx Inc. releases the ISE Design Suite 12.2, an easier-to-use, intuitive, fourth generation of partial reconfiguration design flow offering an improvement to its intelligent clock gating technology. |
| 2010-06-16 | Employing clock gating in ASIC, FPGA designs Employing clock gating in ASIC, FPGA designs |
| 2010-05-06 | FPGA suite packs design preservation capabilities Xilinx releases ISE Design Suite 12 that adds intelligent clock gating technology, advances in timing-driven design preservation, AMBA 4 AXI4-compliant IP support and easier-to-use partial reconfiguration capabilities. |
| 2008-01-15 | Use clock-gating efficiency to reduce power Use clock-gating efficiency to reduce power |
| 2008-10-27 | Saving power in portable apps Know some techniques to minimise power consumption of portable devices and lengthen life spans of batteries. |
| 2007-08-30 | Ultra-low-power DSP design This article presents detailed power results for the optimization of a low-power DSP, specifically by tuning its algorithm, processor architecture, and memory system, as well as through clock gating. |
| 2008-03-04 | Low Power Design For Analogue/Mixed-Signal IP Power reduction and management techniques using multiple clock and power domains and power gating are effective for digital circuits. In analog design, however, lowering power consumption must be considered early in the design phase. |
| 2007-03-28 | Tool automatically adds clock-gating logic to RTL code Tool automatically adds clock-gating logic to RTL code |
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