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| 2011-07-14 | Cadence gains clock optimisation tech with Azuro buy Cadence gains clock optimisation tech with Azuro buy |
| 2010-08-13 | Design suite enhances FPGA partial reconfiguration Xilinx Inc. releases the ISE Design Suite 12.2, an easier-to-use, intuitive, fourth generation of partial reconfiguration design flow offering an improvement to its intelligent clock gating technology. |
| 2007-12-05 | IPextreme brings Motorola's advanced IC tech to market IPextreme has announced that the company is bringing advanced Motorola patented clock generation tech to market that eliminates need for multiple analogue PLLs enabling lower cost and reliable devices. |
| 2005-12-07 | USB-UART bridge integrates FPGA clock generator USB-UART bridge integrates FPGA clock generator |
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