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| 2011-10-26 | Avoiding RTL coding mistakes Here's a discussion on RTL coding styles that lead to increased design cycle time and unnecessary complexity during design closure. |
| 2011-07-29 | ST–Ericsson cuts R&D costs ST–Ericsson's R&D site in Basingstoke, England has been earmarked for closure following the latest cost-cutting plan. |
| 2011-07-15 | Cavium licenses Arteris NoC Interconnect IP Cavium Networks licenses Arteris' FlexNoC network-on-chip interconnect fabric IP that is said to offer faster interconnect operating frequencies and lower power consumption. |
| 2011-04-25 | Seagate gains Samsung HDD for Rs.6000 crore Seagate Technology is set to buy Samsung's HDD business for Rs.6,278.54 crore ($1.375 billion) expecting closure by the end of 2011. |
| 2011-04-15 | Facilitating at-speed test at RTL (Part 2) Find out more about at-speed timing closure rules and at-speed coverage. |
| 2011-03-25 | Uniquify's memory controller IP auto-tunes timing Uniquify's Self-Calibrating Logic makes possible SoC designs that use its memory controller IP to automatically fine-tune critical timing parameters after the SoCs are installed in system boards. |
| 2011-02-21 | Evolution of manufacturing closure for advanced nodes (Part 3 Evolution of manufacturing closure for advanced nodes (Part 3 |
| 2011-02-14 | Evolution of manufacturing closure for advanced nodes (Part 2 Evolution of manufacturing closure for advanced nodes (Part 2 |
| 2011-02-07 | Evolution of manufacturing closure for advanced nodes (Part 1 Evolution of manufacturing closure for advanced nodes (Part 1 |
| 2010-12-10 | Talus IC implementation tool gears for 20nm Magma Design Automation Inc. unveils the Talus ver.1.2, a tool for routing, timing and extraction to aid SoC implementation. |
| 2010-10-26 | Place and route system offers MCMM design closure Place and route system offers MCMM design closure |
| 2010-07-28 | Reap the benefits of a design preservation flow Design preservation can reduce the implementation iterations during the timing closure phase by implementing just the changed modules. |
| 2010-01-05 | Achieving timing closure in basic (PMA direct) functional mode Achieving timing closure in basic (PMA direct) functional mode |
| 2009-12-29 | Timing closure methodology for advanced FPGA designs Timing closure methodology for advanced FPGA designs |
| 2009-11-23 | Dealing with problems during timing closure Dealing with problems during timing closure |
| 2009-09-10 | Will Wipro exit semiconductor IP biz? R&D services provider Wipro Technologies has apparently decided to get out of the semiconductor IP business. |
| 2009-06-01 | Talus 1.1 delivers fast timing closure Talus 1.1 delivers fast timing closure |
| 2009-04-13 | Platform delivers faster verification Synopsys Inc. has unveiled the latest generation of its Discovery Verification Platform. |
| 2009-03-02 | ASIC design guidelines, timing closure techniques ASIC design guidelines, timing closure techniques |
| 2009-01-15 | Atrenta to visit India for design closure seminar Atrenta to visit India for design closure seminar |
| 2008-12-05 | Cadence unveils multi-core design solution The Encounter Digital Implementation System offers new and enhanced implementation and design closure technologies. |
| 2008-10-24 | Accelerating verification closure for complex SoCs, IPs Accelerating verification closure for complex SoCs, IPs |
| 2008-10-01 | IC Compiler features faster runtimes The IC Compiler 2008.09 from Synopsys delivers enhanced design closure and increased automation boost designer productivity. |
| 2006-03-01 | How to achieve fast timing closure on FPGA designs How to achieve fast timing closure on FPGA designs |
| 2008-04-10 | Nokia moves Bochum plant to Romania Nokia Oy and union representatives at the Bochum, Germany plant have agreed on a Rs.1,245.15 crore ($315.4 million) package to soften the blow of the controversial closure of the Finnish group's facility. |
| 2007-03-04 | How to achieve predictable front-end power closure How to achieve predictable front-end power closure |
| 2008-02-05 | Maxim to shut down Dallas fab Seeking to cut costs, Maxim has announced the ramp down and eventual closure of its U.S. wafer fab in Dallas, Texas and the restructuring of certain businesses. |
| 2008-01-29 | Synopsys suite improves signal integrity analysis Synopsys? 2007.12 release of its PrimeTime suite has set new performance standard for both static timing and signal integrity analysis, accelerating turnaround time and design closure for today's nanometer designs. |
| 2007-09-27 | Mentor touts first incremental FPGA synthesis tool Mentor Graphics has released the Precision RTL Plus Synthesis that enables designers to reach timing closure faster, minimise the impact of late cycle design changes and make efficient use of FPGA architectural blocks. |
| 2007-07-11 | Using graph-based synthesis for FPGA timing closure Using graph-based synthesis for FPGA timing closure |
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