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| 2010-08-23 | Upgraded tool suite enhances CPLD design Upgraded tool suite enhances CPLD design |
| 2010-04-08 | Using reference designs in implementing low, high frequency ADCs Designers of digital systems are familiar with implementing the "leftovers" of their digital design by using FPGAs and CPLDs to glue together various processors, memories and standard function components on their PCB. |
| 2008-11-12 | CPLD design and timing CPLD design and timing |
| 2008-09-22 | Zero-power CPLDs enable low-power portable apps Zero-power CPLDs bring the advantages of programmable logic to low-power design. |
| 2001-03-19 | Converting designs from FLASH370i to Ultra37000 devices This application note addresses the issues associated with upgrading a design from a FLASH370 or a FLASH370i CPLD to an Ultra37000 CPLD. |
| 2005-09-01 | The changing face of automotive ECU design The changing face of automotive ECU design |
| 2001-03-30 | Understanding the Warp report file for Ultra37000-devices This application note provides a comprehensive description of the report file generated by the Warp HDL synthesis tool for the Ultra37000 CPLDs. |
| 2001-03-23 | Board layout considerations for ISR programming of Cypress CPLDs This application note provides information regarding board layout and design for In-System Reprogrammable (ISR) programming of Cypress CPLDs from a PC through an ISR cable. |
| 2001-03-20 | Method to instantiate and use a core in Warp with Cypress CPLDs This application note describes in detail how customers can incorporate cores in their system-level designs. It contains a detailed description of the steps required to instantiate VIF files in both VHDL and Verilog designs. |
| 2001-03-20 | Method to instantiate and use a core in Synplify This application note is intended to assist people who use cores for Cypress Semiconductor's CPLDs and compile their design in Synplify. |
| 2001-03-20 | Method to instantiate and use a core in LeonardoSpectrum This application note is intended to assist people who use cores for Cypress Semiconductor's CPLDs and compile their design in LeonardoSpectrum. |
| 2001-03-21 | Method to instantiate and use a core in Warp Enterprise/Professional This application note contains a detailed description of the steps required to instantiate the core contained in the VIF file using the Warp Enterprise/Professional tool. |
| 2001-03-23 | Designing with Cypress in-system reprogrammable (ISR) CPLDs for PC cable programming This application note presents how to design with the Cypress In-System Reprogrammable (ISR) families of CPLDs, which includes the FLASH370i family and the Ultra37000 family, for programming from a PC with the ISR programming cable. |
| 2001-03-28 | Targeting Cypress ISR CPLDs with Synplify 6.0 This application note describes how to effectively design and target Cypress Semiconductor's In-System Reprogrammable (ISR) CPLDs using Synplicity's Synplify and the Warp Release 6.0 for compilation, synthesis and fitting. |
| 2001-04-12 | Configuring Xilinx FPGAs using an XC9500 CPLD and parallel PROM Configuring Xilinx FPGAs using an XC9500 CPLD and parallel PROM |
| 2001-04-12 | Configuring Spartan-II FPGAs from parallel EPROMs This application note describes a simple CPLD-based interface design to configure a Spartan-II device from a parallel EPROM using the Slave Parallel configuration mode. |
| 2002-06-28 | Using in-system programming in boundary scan systems This application note discusses the basic design considerations for in-system programming of multiple XC9500 devices in a boundary scan chain, and shows how to design systems that contain multiple XC9500 devices, as well as IEEE 1149.1-compatible devices. |
| 2002-06-28 | Low power design with CoolRunner-II CPLDs Low power design with CoolRunner-II CPLDs |
| 2002-06-28 | XC1700 and XC18V00 design migration considerations XC1700 and XC18V00 design migration considerations |
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