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| 2007-01-08 | Top 10 methods for ASIC power minimization (1) This is the first of a two-part article focusing on power minimization in deep submicron ASICs. It lists five of ten independent architectural power saving techniques and basic power consumption theories. |
| 2007-01-10 | Top 10 methods for ASIC power minimization (2) This is the second part of a two part article focusing on power minimization in deep submicron ASICs. It focuses on five effective implementation level low power techniques. |
| 2007-09-03 | Structured ASICs- an attractive option for custom IC design Given the increasing NRE charges and long design schedules associated with deep-submicron standard-cell ASICs, the use of structured ASICs for custom IC design is an increasingly attractive option.. |
| 2006-01-01 | Taiwan's ERSO focuses on innovative memory technology As process technologies move into deep-submicron arena, Taiwan makers realise that they have to develop their proprietary technologies in a bid to keep competitiveness. |
| 2000-12-01 | Technique probes deep-submicron test Technique probes deep-submicron test |
| 2001-04-15 | Timing closure in DSM design Timing closure has taken center stage as the toughest challenge for today's deep-submicron designs. Subsequently, the problem of accurate timing verification has become more important than ever before. Can engineers continue to predict the timing of ICs prior to manufacturing as technologies continue to scale? |
| 2001-05-01 | Power distribution for deep-submicron SoC designs Power distribution for deep-submicron SoC designs |
| 2001-10-01 | Reducing power, area in cell-based designs This technical design article describes Prolific Inc.'s automated library generating tool that reduces power consumption and area for cell-based designs in the deep-submicron range. |
| 2001-12-01 | Implementing OLA to remove delays This article addresses the delay problems DSM (deep-submicron) design closure poses and how OLA (open library application programming interface) can be the format to help solve it. |
| 2002-03-01 | Improving accuracy with model-delay library systems This technical article describes the advantage of implementing SPDM (scalable polynomial delay model) over NLDM (non-linear delay model) in attaining accurate deep-submicron modeling results. |
| 2002-04-16 | Modeling less than the 0.13? technology This technical article focuses on the critical problems involved in 0.13? technology and how innovative modeling can effect enhanced process variations on interconnect parasitics. |
| 2005-08-16 | Standard metal enables paradigm shift in ASIC technology Deep-submicron design and manufacturing issues drive the critical need for a new design technology to replace standard cell |
| 2005-08-16 | DFT, DFM tests assure quality SoC design Learn the importance of design-for-manufacturability and design-for-test in ramping up advanced products in deep-submicron technologies |
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