- Article
(49) -
Forum
(0) -
Blog
(0)
total search49 articles
sort by relevance
sort by date
| 2012-05-18 | Design platform targets complex SoC algorithms Design platform targets complex SoC algorithms |
| 2012-04-18 | Achieving early and accurate power analysis RTL power analysis offers the right trade-offs between accuracy and the ability to design for lower power. |
| 2011-11-15 | RTL tech optimised for power-sensitive apps Apache unleashes the register-transfer-language (RTL) Power Model (RPM) claimed as a first-in-class technology geared to optimise power-sensitive applications. |
| 2011-11-03 | Address mixed-signal design issues with assertion-based verification Address mixed-signal design issues with assertion-based verification |
| 2011-06-28 | Improve simulation studies with 3D animation Read about the use of 3D animation in simulation-centric workflows to augment early verification activities, such as those used in model-based design. |
| 2010-01-14 | Tech, tech practice to boost 2010 engineering success Mathworks India Pvt. Ltd managing director, Kishore Rao has identified parallel language, early verification with Model-Based Design as cornerstones of engineering success in 2010. |
| 2009-06-23 | Start-up to demo asynchronous synthesis tool Tiempo will demonstrate the first asynchronous synthesis tool that operates from standard languages at DAC. |
| 2009-05-21 | Spirit announces release of SystemRDL Spirit Consortium has approved SystemRDL, a language for the design and delivery of registers to be used in IP blocks. |
| 2008-02-18 | Multi-language SoC verification for multi-site projects Multi-language SoC verification for multi-site projects |
| 2008-11-20 | Create IP for system generator for DSP Read about a graphical design environment called Simulink and a mathematical modelling language called Matlab. |
| 2006-10-25 | Using block diagrams as a system design language Using block diagrams as a system design language |
| 2005-05-18 | MATLAB: The sleeper ESL hit The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow. |
| 2005-05-18 | MATLAB: The sleeper ESL hit The article discusses MATLAB, a new design entry language for next-generation SoCs. It looks at its advantages versus SystemC and SystemVerilog and its applicable design flow. |
| 2006-07-21 | Using UML for SoC hardware/software design Using UML for SoC hardware/software design |
| 2006-07-21 | Using UML for SoC hardware/software design Using UML for SoC hardware/software design |
| 2008-07-04 | Design tool includes upgrades focused on usability Design tool includes upgrades focused on usability |
| 2006-05-05 | Design your own memory using ABEL Design your own memory using ABEL |
| 2001-11-01 | An introduction to Esterel Esterel is a system-design language that can be used to generate complex state machines automatically. This article offers an overview of the syntax and usage. |
| 1998-05-02 | Designing real-time systems with UML, Part 3 This article wraps up Douglass' series on the Unified Modelling Language with a focus on architectural, mechanistic, and detailed design. |
| 2004-03-01 | Get to know Model Checking Model checking has proven to be a successful technology to verify requirements and design for a variety of real-time embedded and safety-critical systems. Here's how it works. |
| 2005-01-02 | Back to the language roots Back to the language roots |
| 2006-03-01 | Demystifying UML The Unified Modelling Language has the potential to change embedded systems design but most working engineers don't know what it is or how it works. This recognised expert wrote the book on UML and explains how it applies to today's developers. |
| 2006-05-05 | Design your own memory using ABEL Design your own memory using ABEL |
| 2007-08-04 | Use AADL to analyze and design embedded systems Use AADL to analyze and design embedded systems |
| 2007-11-23 | Mentor, MathWorks collaborate on optimised FPGA design flow Mentor, MathWorks collaborate on optimised FPGA design flow |
| 2007-05-17 | Multi-core pushes RTOS, tool revisions RTOS and tool providers are improving model-driven design, virtual prototyping and C-language compilation to spur multi-core programming and debugging. |
| 2007-04-02 | FPGA use in HPCs faces bottleneck problems Current FPGA synthesis, placement and routing tools are written for hardware designers, not software programmers. A new generation of ESL C-language compilers is attempting to bridge the gap. |
| 2007-02-27 | EDA 'troublemakers' debate at DVCon EDA vendor The annual "EDA Bigwigs" panel at the Design and Verification Conference (DVCon) was renamed the "Troublemaker's Panel" this year for good reason. Confronted with provocative questions, DVCon EDA vendor representatives debated topics such as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India. |
| 2007-02-21 | SystemVerilog fails to deliver on design SystemVerilog fails to deliver on design |
| 2006-11-16 | Revised VHDL spec boosts IP security The Accellera standards organisation has approved a revised version of the VHDL specification, marking a huge step forward for the design language. Pending IEEE approval, the revision will bring Property Specification Language (PSL) assertions into VHDL and will add capabilities for IP encryption. |
Most Popular Articles
Search EE Times India
Max's Cool Beans
Strange modes of transport and other "stuff"
Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...
