- Article
(28) -
Forum
(0) -
Blog
(0)
total search28 articles
sort by relevance
sort by date
| 2012-04-04 | Freescale, Mathworks optimise automotive design Freescale, Mathworks optimise automotive design |
| 2011-11-03 | ARM acquires design optimisation firm, Prolific ARM acquires design optimisation firm, Prolific |
| 2011-07-14 | Cadence gains clock optimisation tech with Azuro buy Cadence gains clock optimisation tech with Azuro buy |
| 2011-02-10 | Platform enables multicore optimisation tech Platform enables multicore optimisation tech |
| 2011-01-17 | Design optimisation tool offers feasibility analysis Design optimisation tool offers feasibility analysis |
| 2010-03-05 | MCU sub-system tipped flash-based FPGAs eases design MCU sub-system tipped flash-based FPGAs eases design |
| 2010-01-22 | Think optimal algorithms, data structure designs Optimisation of applications should not be a final step in project development, but rather an ongoing design philosophy that begins from the planning stages all the way through completion. |
| 2009-12-08 | ASML, ST speed sub-30nm development The silicon printing optimisation with lithography control and integrated design (SOLID) project seeks sub-30nm node solutions. |
| 2009-10-16 | Autosar ushers in auto design optimisation (Part 1 Autosar ushers in auto design optimisation (Part 1 |
| 2009-04-16 | Full-chip synthesis tool for advanced ICs upgraded Magma Design Automation Inc. has unveiled an upgraded version of Talus Design. |
| 2009-01-30 | Noise optimisation in sensor signal-conditioning ICs Noise optimisation in sensor signal-conditioning ICs |
| 2009-01-28 | Optimising video analytics on a DSP Here are design and optimisation strategies for a practical video analytics implementation running on a DSP. |
| 2008-12-03 | Fastest electromagnetic simulator debuts in India Concerto v7 introduces numerous improvements to accelerate the speed of simulation and optimisation. |
| 2008-01-15 | Use clock-gating efficiency to reduce power Clock-gating is an accepted design technique for optimising power, and can be applied at the system level. |
| 2008-10-07 | Advancements call for new routing technology Routing technology must be fully integrated with placement, clock tree, and multi-corner multi-mode optimisation in order to achieve higher QoR. |
| 2008-08-29 | MIT, UCLA adopt Magma's software Titan Analog Migration is focused on analogue/mixed-signal design optimisation and porting. |
| 2006-11-08 | Video-based vehicle safety systems optimisation Video-based vehicle safety systems optimisation |
| 2008-03-10 | Robust controller design using multi-objective optimisation Robust controller design using multi-objective optimisation |
| 2008-06-12 | DSP power optimisation methods for wireless applications DSP power optimisation methods for wireless applications |
| 2008-01-17 | Simulation of Proprietary Low Power Wireless Systems Proposes a simulation tool that designers can use for developing proprietary short-range wireless systems, while keeping within local regulatory requirements and design parameters. |
| 2008-03-10 | HEADLINE: Robust controller design using multi-objective optimisation HEADLINE: Robust controller design using multi-objective optimisation |
| 2007-03-28 | Tool automatically adds clock-gating logic to RTL code Claiming breakthrough technology in IC power optimisation, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code. |
| 2007-02-12 | Optimisation tool supports spatial modelling Optimisation tool supports spatial modelling |
| 2007-01-19 | Clear Shape, STARC partner in DFM flow Clear Shape Technologies Inc. announced a partnership with STARC to jointly develop, validate and deploy a variability-aware DFM flow. The flow includes InShapeT for systematic variability analysis that enables optimisation during implementation using commercial routing tools. |
| 2006-09-21 | Acuma tool implements yield improvement Nannor Technologies Inc. has announced that its upgraded Acuma tool reduces semiconductor design iterations and manufacturing costs by revealing yield-sensitive areas of the design and implementing yield improvement at the design stage. |
| 2006-07-21 | Sequence Design to demo clock power analysis at DAC Sequence Design to demo clock power analysis at DAC |
| 2006-03-31 | ZenTime products address specific cell design issues ZenTime products address specific cell design issues |
| 2006-02-06 | Cadence offers silicon-proven full-chip optimisation system Cadence offers silicon-proven full-chip optimisation system |
--- total search 28 articles, total 1 pages, The 1 Page ---
1
Most Popular Articles
Search EE Times India
Max's Cool Beans
Strange modes of transport and other "stuff"
Someone just pointed me at a YouTube video that claims to show the world's first e-powered multicopter flight...
